Near-Memory Polynomial Processing for Lower FHE Data Movement
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Solution Overview
Problem
Fully homomorphic encryption (FHE) operations are time-consuming and inefficient due to the need for large off-chip data transfer, as conventional hardware like CPUs and GPUs struggle with processing long and wide polynomials, and even ASICs with large on-chip memory are insufficient for storing large keys.
Innovation Solution
A near memory processing (NMP) device architecture with enclaves and tiles, utilizing DRAM banks and processing elements to perform operations on decomposed polynomial coefficients, enabling parallel processing and reducing data movement by leveraging DRAM's high bandwidth and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hardware (CPU/GPU) is used for FHE operations, then general-purpose computing is maintained, but processing speed is orders of magnitude slower and on-chip memory is insufficient
Solution Approach 1:
The patent segments the FHE processing system into specialized functional units including polynomial processing units, key generation units, and encryption/decryption units. Each unit is optimized for specific operations, allowing parallel processing of different polynomial operations simultaneously, thereby achieving both versatility and high speed.
Solution Approach 2:
The patent transitions from traditional von Neumann architecture to a memory-centric architecture where processing units are distributed across multiple memory banks. This dimensional change allows data to be processed in-place within memory, eliminating the bottleneck of data transfer between CPU and memory while maintaining general-purpose computing capabilities.
2Productivity
If ASIC with large on-chip memory is used, then FHE operation speed is improved, but on-chip memory is still insufficient for storing large keys requiring off-chip data streaming
Solution Approach 1:
The patent merges the memory storage function with the processing function by integrating polynomial processing units directly within the memory structure. This allows keys and large polynomial data to be stored in memory banks and processed in-place, eliminating the need for separate large on-chip memory while maintaining high-speed processing capability.
Solution Approach 2:
The patent introduces memory banks as intermediary structures that serve both as storage and processing substrates. These memory banks act as intermediaries between off-chip memory and processing units, allowing data to be fetched once and processed multiple times without repeated off-chip access, thereby providing sufficient effective memory capacity for large keys.
3Quantity of substance
If off-chip data transfer is used for FHE operations, then data storage capacity is sufficient, but data transfer time and energy consumption increase significantly
Solution Approach 1:
The patent implements preliminary action by pre-fetching and pre-processing data within the memory hierarchy before it is needed for computation. Memory banks prepare polynomial coefficients and key data in advance, organizing them for efficient processing, which eliminates the need for time-consuming off-chip data transfer during actual FHE operations.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining data in the memory-processed state throughout the computation pipeline. Once data is loaded into memory banks, it remains there and is continuously processed through various polynomial operations without being transferred out, ensuring that the data stays in the system and is reused efficiently across multiple operations.
Data Source
AI summary
Provided are a near memory device, system, and method for processing coefficient elements resulting from decomposition of polynomials. The near memory device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. A tile includes a memory and a processing element to perform operations on decomposed coefficients stored in the memory of the tile. An enclave controller in an enclave of the enclaves receives an operation for coefficients of a polynomial. Each of the coefficients are decomposed into a number of levels of coefficient elements. The enclave controller distributes the coefficient elements to the tiles in the enclave to have processing elements of the tiles load and process the coefficient elements and store the processed results.