Near-Memory Matrix Computation Using Alternating-Cycle SPRAM
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Solution Overview
Problem
Integrated circuits face challenges with large local memory requirements and bottlenecks in accelerator-based computations due to the use of dual-port RAM, which are costly and inefficient for matrix operations.
Innovation Solution
Implementing single-port RAM (SPRAM) with alternating clock cycles for read and write operations, reducing memory size and power consumption while maintaining performance by doubling the width and halving the depth of SPRAM compared to DPRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port RAM is used for local memory in accelerator-based computations, then read and write operations can occur simultaneously, but memory size and cost increase significantly
Solution Approach 1:
The patent implements single-port RAM with alternating clock cycles where even cycles are dedicated to write operations and odd cycles to read operations. This periodic allocation of the single port allows the memory to serve both read and write functions sequentially, achieving the functionality of dual-port RAM while using only single-port memory cells, thus reducing memory size by 50%.
2Productivity
If dual-port RAM is used for local memory, then simultaneous read and write operations are enabled, but power consumption increases
Solution Approach 1:
By alternating between write operations on even clock cycles and read operations on odd clock cycles, the single-port RAM ensures that only one operation is active at any given time. This eliminates the simultaneous switching activity that causes high dynamic power consumption in dual-port RAM, achieving 30% power reduction while maintaining computational throughput.
3Quantity of substance
If single-port RAM is used instead of dual-port RAM, then memory size is reduced by 50%, but read and write operations cannot occur simultaneously
Solution Approach 1:
The patent implements a periodic operation scheme where the single-port RAM alternates between write operations on even clock cycles and read operations on odd clock cycles. This time-division multiplexing allows the memory to handle both read and write traffic efficiently, maintaining computational throughput comparable to dual-port RAM while achieving 50% memory size reduction.
Solution Approach 2:
The patent dynamically adjusts the memory operation mode based on the computational phase. During matrix multiplication, the system alternates between loading input matrices (write-intensive) and reading results (read-intensive), and the single-port RAM adapts its operation accordingly through alternating clock cycles, optimizing performance for each phase.
4Productivity
If local memory is made larger to accommodate matrix operations, then computation capacity increases, but cost and bottleneck effects worsen
Solution Approach 1:
The patent changes the fundamental parameter of memory port configuration from dual-port to single-port, combined with alternating clock cycle operations. This parameter change allows the same physical memory size to achieve the same computational throughput as larger dual-port memory, reducing both cost and bottleneck effects while maintaining matrix computation capacity.
Data Source
AI summary
Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.