Memory Operations Management With OS-Accessible Near Memory Caching
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Solution Overview
Problem
The use of DDR SDRAM as cache memory for CPUs is expensive and not accessible by the operating system, contributing significantly to datacenter server costs, and existing technologies do not efficiently utilize near memory as allocatable system memory.
Innovation Solution
Implement memory tiering where near memory is used as a swap buffer for far memory, allowing it to be visible and accessible by the operating system, with a hardware memory controller managing swapping operations at a cache-line granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DDR SDRAM is used as cache memory for CPU, then caching performance is improved, but system cost increases significantly
Solution Approach 1:
The near memory is designed to serve multiple functions: it acts as both CPU cache memory and as allocatable system memory accessible by the operating system. This multi-functionality allows the same hardware resource to provide caching performance while also being available for general system use, thereby reducing the need for separate dedicated cache memory and lowering overall system cost.
Solution Approach 2:
The system dynamically manages the near memory between CPU cache operations and OS-accessible system memory operations. The memory controller logic circuitry dynamically determines whether to service CPU cache requests or OS memory requests based on current system needs, allowing flexible adaptation to different operational states and optimizing both performance and resource utilization.
2Speed
If DDR SDRAM is used as dedicated cache memory, then CPU access speed is improved, but operating system accessibility is lost
Solution Approach 1:
The near memory is designed to serve multiple functions: it acts as both CPU cache memory and as allocatable system memory accessible by the operating system. This multi-functionality allows the same hardware resource to provide caching performance while also being available for general system use, thereby reducing the need for separate dedicated cache memory and lowering overall system cost.
Solution Approach 2:
The memory controller logic circuitry acts as an intermediary between the CPU and the near memory, as well as between the operating system and the near memory. It receives requests from both the CPU (for cache operations) and the operating system (for memory access), and intelligently routes and services these requests appropriately, enabling the near memory to be simultaneously accessible for both CPU caching and OS memory management.
3Adaptability or versatility
If near memory is made accessible by operating system, then memory allocatability is improved, but CPU cache performance may deteriorate
Solution Approach 1:
The system dynamically manages the near memory between CPU cache operations and OS-accessible system memory operations. The memory controller logic circuitry dynamically determines whether to service CPU cache requests or OS memory requests based on current system needs, allowing flexible adaptation to different operational states and optimizing both performance and resource utilization.
Solution Approach 2:
The system incorporates feedback mechanisms where the memory controller logic circuitry monitors request patterns and system state, and adjusts its behavior accordingly. When CPU cache performance is prioritized, the controller can allocate the near memory primarily for cache operations; when system memory needs are higher, it can allocate more capacity to OS-accessible regions, thus maintaining optimal performance across different workloads.
Data Source
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Figure 3A~3B
AI summary
Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory (151), data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in a second memory (153) that contains data corresponding to the system memory section and retrieving the data from the identified memory location.