Ratioless Near-Threshold Level Translator for Node Contention
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Solution Overview
Problem
Existing level translators face challenges in managing contentious internal nodes at near-threshold levels, particularly when scaling down, due to the use of transistors of differing sizes, which leads to performance issues and variability among individual transistors, especially in interfaces with a large number of signal lines.
Innovation Solution
Implementing a ratioless near-threshold level translator using transistors of substantially the same size, with configurations that include pass and keep transistors of the same type, managed by complementary output signals to minimize contention and leakage, allowing for scalable and reduced circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors of differing sizes are used to manage contentious internal nodes, then voltage level translation can be achieved, but performance variability and manufacturing precision deteriorate due to transistor size variations
Solution Approach 1:
The patent applies homogeneity by using transistors of the same size throughout the level translator circuit. Specifically, all pass transistors and keep transistors are designed with identical width-to-length ratios, eliminating the need for precise transistor sizing and matching. This homogeneous design ensures consistent performance across process variations and simplifies manufacturing while maintaining reliable voltage level translation.
2Reliability
If transistor sizes are increased to reduce contention effects, then voltage level translation reliability improves, but device area increases
Solution Approach 1:
The patent changes the parameter approach by eliminating the need for large transistor sizes to manage contention. Instead of increasing transistor dimensions, the invention uses a ratioless design where pass transistors and keep transistors are controlled by complementary signals, allowing proper contention management with minimum-sized transistors. This parameter change from size-based to signal-based control reduces the overall circuit area while maintaining translation reliability.
3Manufacturing precision
If transistors of the same size are used, then manufacturing precision and scalability improve, but managing contentious nodes becomes more difficult
Solution Approach 1:
The patent applies segmentation by dividing the level translator into distinct functional blocks: pass transistor sections and keep transistor sections. Each section is independently controlled by complementary output signals, allowing the circuit to manage contentious nodes through structured signal distribution rather than complex transistor sizing. This segmented architecture simplifies the design while maintaining effective contention management.
4Reliability
If larger transistors are used to ensure proper voltage translation, then translation reliability improves, but the circuit becomes less scalable
Solution Approach 1:
The patent applies universality by creating a level translator design that functions correctly with minimum-sized transistors, making the circuit universally applicable across different process nodes and scaling conditions. The ratioless architecture with complementary signal control ensures proper voltage translation regardless of transistor size, allowing the same design to be scaled down to smaller process technologies without requiring redesign or larger device dimensions.
Data Source
AI summary
An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.