Conductive Neck Layer Geometry for Bit Line Contact Yield

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Solution Overview

Problem

Challenges arise during the scaling-down process of semiconductor devices, including issues related to quality, yield, performance, and reliability, which are not adequately addressed by existing technologies.

Innovation Solution

A semiconductor device design featuring a conductive neck layer with a wider top surface than bottom surface, positioned between bit line structures, enhancing the overlapping window for the conductive neck layer and landing pad, thereby reducing defects and complexity in fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the dimensions of semiconductor devices are scaled down, then computing ability is improved, but quality, yield, performance, and reliability deteriorate

Engineering Contradiction:

Improvecomputing abilityVSAvoiddevice quality and yield

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The conductive neck layer is divided into two distinct width portions: a first width at the contact layer interface and a second width at the top surface. This segmentation allows each portion to be optimized independently - the narrower bottom portion reduces parasitic capacitance for faster switching, while the wider top portion ensures reliable electrical connection and positioning tolerance, thus resolving the contradiction between scaling down for computing ability and maintaining reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the conductive neck layer are given different dimensional characteristics - the bottom portion has a narrower width optimized for electrical performance and speed, while the top portion has a wider width optimized for connection reliability and alignment tolerance. This local differentiation allows the device to achieve both high computing ability through scaling and maintained reliability through localized optimization

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If the overlapping window for conductive neck layer and landing pad is increased, then fabrication defects are reduced, but device area increases

Engineering Contradiction:

Improvefabrication defect reductionVSAvoiddevice area

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The conductive neck layer extends beyond the minimum required area for electrical connection by providing a wider top width portion. This excessive action in one dimension (width at top surface) creates a larger overlapping window with the landing pad, improving manufacturing precision and reducing alignment defects, while the narrowing at the bottom keeps the overall device area constrained

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS20250293160A1Semiconductor device with neck layer and method for fabricating the same

Publication Date: 2025.09.18 NAN YA TECH

AI summary

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; at least two bit line structures positioned on the substrate; a contact layer positioned on the substrate and between the at least two bit line structures; and a conductive neck layer positioned on the contact layer and between the at least two bit line structures. A width of a top surface of the conductive neck layer is greater than a width of a bottom surface of the conductive neck layer.