Neck Saddle Fin Memory Cell Reduces Wordline Disturb
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Solution Overview
Problem
As semiconductor memory devices become more integrated, the short channel effect and parasitic capacitance coupling between wordlines and adjacent floating gates in recessed channel array transistors (RCATs) lead to reliability issues such as Edge Wordline Disturb, where adjacent cells experience unwanted threshold voltage shifts, particularly in NAND flash memory.
Innovation Solution
The introduction of neck saddle fins with a narrower and concave profile, combined with heavier implant modifications, helps mitigate the adjacent wordline disturb issue by increasing the effective channel length and improving electrical performance metrics like Vt/SVt, Ids, and Ids/Ioff ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell size is reduced to increase integration, then productivity increases, but the short channel effect worsens and manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional recessed channel structure. By forming a recess in the substrate and placing the gate within this recess, the channel extends vertically into the substrate, effectively increasing the channel length without increasing the planar footprint. This dimensional change allows continued scaling while maintaining control over the diffusion layer depth and reducing the short channel effect.
2Productivity
If the channel length is reduced to increase integration, then productivity increases, but the short channel effect worsens
Solution Approach 1:
The recessed channel structure extends the channel length in the vertical dimension into the substrate, compensating for the reduced planar channel length. This allows the transistor to maintain adequate effective channel length for reliable operation while achieving higher integration density through reduced cell footprint.
Solution Approach 2:
The gate structure is nested within the recess formed in the substrate. This nesting approach allows the gate to be positioned deeper in the structure, increasing the distance between source and drain regions and effectively lengthening the channel path without increasing the surface area of the memory cell.
3Reliability
If conventional RCAT structure is used to extend channel length, then short channel effect improves, but parasitic capacitance coupling between wordlines and adjacent floating gates increases
Solution Approach 1:
The patent introduces asymmetric neck fins with different widths at different heights, creating a non-uniform channel structure. The narrower neck region at specific heights increases resistance to parasitic coupling between adjacent wordlines and floating gates, while the overall recessed structure maintains sufficient channel length to control the short channel effect.
Solution Approach 2:
The neck fin structure creates localized regions of different channel widths. The narrower neck regions are strategically positioned to reduce parasitic capacitance coupling in specific areas, while other regions maintain adequate width for current flow. This local variation in geometry allows simultaneous optimization of both short channel control and parasitic reduction.
4Reliability
If deeper fin structure is formed to reduce parasitic capacitance, then wordline disturb improves, but manufacturing complexity increases and array bottom damage risk increases
Solution Approach 1:
The recess is formed in the substrate before the fins are created. This preliminary action establishes the depth constraint for the fin structure, ensuring that fins do not extend too deeply and potentially damage the array bottom. The pre-formed recess acts as a physical guide that limits fin depth while still allowing sufficient depth to reduce parasitic capacitance.
Data Source
AI summary
A semiconductor device with neck fins comprises a substrate, a plurality of fins having a lower portion and a neck upper portion on the substrate, and insulators disposed between each fin and flush with the lower portion of the fins.