Necked Fin Structure for Lower External Resistance in Multi-Gate Transistors
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Solution Overview
Problem
The challenge of reducing external resistance (Rext) in multi-gate transistors, such as fin-FET and tri-gate transistors, has not been adequately addressed in conventional manufacturing processes, despite efforts to improve contact metals and dopant activation.
Innovation Solution
The implementation of semiconductor devices with necked semiconductor bodies, featuring different fin widths in the channel and under the spacer, which includes forming sidewall spacers over only a portion of the source and drain regions, allowing for optimized fin dimensions to reduce external resistance and improve drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and process complexity is simplified, but external resistance cannot be adequately reduced
Solution Approach 1:
The patent applies local quality by creating a necked region with different dimensions than the rest of the semiconductor body. Specifically, the semiconductor body has a first width at the source/drain regions and a second, narrower width at the channel region, allowing different areas to be optimized for different functions: wider source/drain for lower resistance and narrower channel for better short-channel control
Solution Approach 2:
The patent changes the geometric parameters of the semiconductor body by introducing a necked region with reduced width compared to the source/drain regions. This parameter change enables simultaneous optimization of resistance (through wider source/drain) and short-channel effects (through narrower channel), resolving the contradiction between ease of manufacture and external resistance performance
2Productivity
If feature dimensions are scaled down to increase device density, then capacity is improved, but external resistance constraints become overwhelming
Solution Approach 1:
The patent segments the semiconductor body into distinct regions with different widths: wider source/drain regions for low resistance and a narrower channel region for high-density integration. This segmentation allows each region to be optimized independently, maintaining low external resistance while achieving high device density through scaled dimensions
Solution Approach 2:
By applying local quality with different widths in different regions, the patent enables the source/drain regions to provide low resistance paths while the scaled-down channel region maintains high density. The necked configuration locally optimizes each region's function, resolving the contradiction between productivity and reliability
3Device complexity
If multi-gate transistors are fabricated with conventional processes, then manufacturing is simplified, but the tradeoff between short channel effects and external resistance cannot be optimized
Solution Approach 1:
The patent uses local quality to create a necked semiconductor body with different widths in different regions, allowing the source/drain regions to be wider for lower resistance while the channel region is narrower for better short-channel control. This local differentiation optimizes the tradeoff without requiring complex multi-step fabrication processes
Solution Approach 2:
By changing the geometric parameters to create a necked configuration, the patent enables simultaneous optimization of short-channel effects and external resistance. The parameter change from uniform width to varied width allows each region to perform its function optimally, improving reliability without increasing device complexity
Data Source
AI summary
Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.