Necked Fin Structure for Lower Resistance Multi-Gate Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices leads to overwhelming constraints on external resistance (Rext), and existing techniques have not adequately addressed the need for improved Rext reduction while optimizing performance for both high-performance and low-power devices.
Innovation Solution
The implementation of semiconductor devices with necked semiconductor bodies, featuring different fin widths in the channel and under the spacer, and methods to form semiconductor bodies of varying widths, which include forming sidewall spacers over only a portion of the source and drain regions, allowing for optimized fin dimensions to reduce external resistance and improve drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistors are scaled down to increase device density, then device capacity increases, but external resistance constraints become overwhelming
Solution Approach 1:
The patent applies local quality by creating a necked semiconductor body with different widths at different locations. The channel region has a first width optimized for device density and scaling, while the source and drain regions have a second width (greater than the first) optimized for reducing external resistance. This local differentiation allows each region to be optimized for its specific function without compromise.
Solution Approach 2:
The patent transitions from a uniform two-dimensional cross-section to a three-dimensional structure with varying width along the vertical axis. The necked body creates different cross-sectional areas at different heights, with the channel region having a smaller cross-section than the source and drain regions, thereby adding a dimensional aspect to the semiconductor body geometry.
2Quantity of substance
If transistor dimensions are reduced to increase device count, then chip capacity increases, but drive current optimization becomes increasingly difficult
Solution Approach 1:
The patent applies local quality by creating a necked semiconductor body with different widths at different locations. The channel region has a first width optimized for device density and scaling, while the source and drain regions have a second width (greater than the first) optimized for reducing external resistance. This local differentiation allows each region to be optimized for its specific function without compromise.
3Ease of manufacture
If conventional fabrication processes are used for multi-gate transistors, then manufacturing simplicity is maintained, but external resistance reduction is insufficient
Solution Approach 1:
The necked semiconductor body structure is formed preliminarily before the formation of the gate electrode and channel region. By pre-shaping the semiconductor body with the desired width variations, subsequent fabrication steps can proceed with conventional processes while inheriting the resistance-reducing geometry, thus maintaining ease of manufacture while improving external resistance characteristics.
Data Source
AI summary
Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.