Negative-Bias SPAD Quenching Circuit for High-Light Count Rates

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Solution Overview

Problem

Current photodetection pixels using single photon avalanche diodes (SPADs) face limitations in high light conditions due to saturation, which leads to reduced count rates and instability issues in complex active reset circuits, affecting quantum efficiency and area usage.

Innovation Solution

A SPAD pixel design featuring a quench transistor in high-impedance mode, a recharge transistor in parallel for active recharging, and an adjustable delay circuit to manage the feedback signal for efficient quenching and recharging, integrated within a stacked die arrangement to maintain high count rates without saturation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If passive quenching with source-drain resistance is used, then the circuit is simple, but the dead time is long and saturation occurs in high light conditions

Engineering Contradiction:
Improvecircuit complexityVSAvoidcount rate
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic switching between high-impedance and low-impedance states using transistors controlled by the inverter output. The quench transistor switches to low-impedance state during avalanche to quickly quench the event, while the recharge transistor switches to low-impedance state after delay to rapidly recharge the SPAD. This dynamic impedance switching resolves the contradiction by providing simple passive quenching structure with active rapid recovery capability, achieving high count rates without complex continuous active reset circuits.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs periodic action through the delay circuit that introduces a controlled time delay before activating the recharge transistor. This periodic recharge mechanism allows the SPAD to recover systematically after each avalanche event, preventing saturation in high light conditions while maintaining circuit simplicity. The delay ensures proper timing between quenching and recharging phases.

Inventive Principle:
Principle #19Periodic action

2Productivity

If active reset with feedback is used, then the count rate increases and saturation is avoided, but the circuit area increases and quantum efficiency decreases

Engineering Contradiction:
Improvecount rateVSAvoidpixel area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the quenching and recharging functions into a single integrated circuit block with shared transistors and control logic. The same inverter output controls both the quench transistor during avalanche and the recharge transistor after delay. This merging reduces the overall circuit area compared to separate active reset circuits while maintaining high count rate performance through coordinated transistor switching.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The delay circuit serves multiple functions: it controls the timing of the recharge transistor activation, provides implicit dead time management, and coordinates the recovery phase without requiring separate control circuits. This multi-functionality reduces the overall circuit area while achieving the desired count rate performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of time

If active recharge with delay circuit is used, then the dead time is reduced and high count rates are achieved, but the circuit complexity increases

Engineering Contradiction:
Improvedead timeVSAvoidcircuit complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The delay circuit is pre-configured with fixed delay characteristics determined during circuit design and fabrication. This preliminary setup eliminates the need for complex real-time control logic during operation, as the recharge timing is automatically determined by the pre-established delay circuit parameters. The dead time is thus reduced without requiring complex adaptive control mechanisms.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves stable high count rates in high light conditions with reduced area usage and improved quantum efficiency by enabling quick active recharging and precise delay control, avoiding saturation and maintaining maximum count rates.

Implementation Method 1

When a photon-generated carrier (via the internal photoelectric effect) is injected into the depletion region of the PN junction, a self-sustaining avalanche ensues

Methodology Applied
Scientific EffectInternal photoelectric effect: Photoelectric Effect

Implementation Method 2

a self-sustaining avalanche ensues, and detection of current output as a result of this avalanche can be used to indicate detection of the photon

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS20240145503A1Active recharge quenching circuit for negative bias spad
Publication Date: 2024.05.02 STMICROELECTRONICS (RES & DEV) LTD
  • US20240145503A1 patent drawing
  • US20240145503A1 patent drawing
  • US20240145503A1 patent drawing

AI summary

Disclosed herein is a single photon avalanche diode (SPAD) pixel for use in time-of-flight imaging. This pixel includes a SPAD having a cathode connected to a first node and an anode coupled to first negative voltage. A transistor circuit in the pixel includes a quench transistor connected between a supply voltage node and a second node, the quench transistor controlled by a quench control signal to operate in a high-impedance mode, and a recharge transistor connected in parallel with the quench transistor between the supply voltage node and the second node, the recharge transistor controlled by a feedback signal. The pixel also includes a readout inverter generating an output signal based upon a voltage at the first node and an adjustable delay circuit generating the feedback signal based upon the output signal, the feedback signal being delayed with respect to the output signal.