Negative Biased Substrate for Stacked Image Sensor Pixels
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Solution Overview
Problem
Existing image sensors face challenges in reducing size and improving performance due to increased complexity and cost from methods to reduce image lag, such as boosting floating diffusion voltage or increasing voltage swing of the transfer transistor, which require additional circuitry and metal lines.
Innovation Solution
Implementing a stacked image sensor with separately biased chips, where the pinned photodiode is biased at a negative voltage compared to the floating diffusion, improving image charge transfer efficiency without the need for additional high voltage supplies or circuitry, thus reducing image lag and readout noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If floating diffusion voltage is boosted to reduce image lag, then image lag is reduced, but additional boost line and metal line are required which increases pixel cell size
Solution Approach 1:
The patent changes the voltage parameter by applying a negative bias voltage to the substrate instead of boosting the floating diffusion voltage. This parameter change achieves image lag reduction through a different voltage control mechanism that does not require additional metal lines or boost lines, thereby maintaining pixel cell size while improving performance
2Object-affected harmful factors
If voltage swing of transfer transistor is increased to reduce image lag, then image lag is reduced, but additional circuitry is required which increases pixel size, cost and complexity
Solution Approach 1:
The patent applies a negative bias voltage to the substrate, changing the voltage parameter to achieve better image charge transfer efficiency and reduced image lag. This approach eliminates the need for additional circuitry such as voltage swing enhancement circuits, thereby reducing pixel cell complexity and cost while maintaining the image lag reduction benefit
Data Source
AI summary
A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.