Negative Bit Line Voltage for Memory Cell Program Time Reduction
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Solution Overview
Problem
Existing memory devices face challenges in accurately programming memory cells with increased data states, leading to longer program times and interference from neighboring word lines, particularly in 3D memory structures.
Innovation Solution
The implementation of an enhanced step-up program bias using a negative bit line voltage during the program pulse, allowing for a larger program pulse magnitude and delayed verify tests, reduces the number of program loops required to achieve the desired threshold voltage, thereby shortening the program time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a larger program pulse magnitude is used to increase threshold voltage faster, then program time is reduced, but interference from neighboring word lines increases
Solution Approach 1:
The patent applies different voltages to different word lines during the programming operation. The selected word line receives a high program voltage to achieve fast programming, while neighboring word lines receive inhibit voltages to prevent interference. This localized voltage application allows the system to benefit from fast programming without suffering from neighbor disturb effects.
Solution Approach 2:
The patent applies inhibit voltages to neighboring word lines before and during the programming pulse application. This preliminary anti-action prevents the neighboring word lines from being affected by the large program pulse, thereby eliminating the harmful interference effect before it can occur.
2Object-affected harmful factors
If incremental step pulse programming is used to reduce interference, then program time increases
Solution Approach 1:
Instead of gradually increasing the program voltage in small steps (incremental step pulse programming), the patent inverts the approach by applying a large program voltage pulse immediately while using inhibit voltages on neighboring word lines. This reversal allows fast programming without the time penalty of incremental steps, while still preventing interference through the inhibit voltage mechanism.
3Measurement precision
If verify tests are performed after each program loop to ensure accuracy, then program time increases
Solution Approach 1:
The patent performs verify tests selectively rather than after every program loop. By using the inhibit voltage mechanism to ensure accurate programming, the system can skip intermediate verify tests and only perform verification at critical points, thereby reducing the time spent on verification while maintaining programming accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster programming of memory cells by increasing the threshold voltage in fewer program loops, reducing interference and program time, while maintaining precise control over data states.
Implementation Method 1
enhanced step-up program bias using a negative bit line voltage during the program pulse
Data Source
AI summary
Apparatuses and techniques are described for reducing the program time for a set of memory cells by using an enhanced step up of a program bias. A program operation includes a first pass in which memory cells are programmed to intermediate states and a second program pass in which the memory cells are programmed from an erased state and the intermediate states to final states. In the first program pass, program time can be reduced by applying an enhanced program bias step up to memory cells of the highest intermediate state in a single program loop, for example. The enhanced program bias step up can be achieved by applying a negative bit line voltage and can be triggered when the memory cells assigned to the second highest intermediate state reach a program milestone such as completing programming.