Negative Bit Line Write Assist for SRAM Voltage Scaling
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Solution Overview
Problem
The reduction of SRAM core voltage has lagged behind logic voltage, limiting semiconductor chip power consumption improvement due to increased threshold voltage variations and capacity requirements, leading to write failure issues in SRAM cells where the pass gate transistor cannot overpower the pull-up transistor.
Innovation Solution
A negative bit line write assist system and method that employs an array voltage supply and distributed capacitance to generate a negative bit line voltage during write operations, using a bit line voltage unit and upper metal layer capacitance to enhance write assist capabilities without increasing layout area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SRAM core voltage is reduced to improve power consumption, then power consumption decreases, but write failure occurs due to increased threshold voltage variations and inability of pass gate transistor to overpower pull-up transistor
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a voltage higher than the normal write voltage before the write operation. This pre-charging creates a voltage headroom that enables the pass gate transistor to overcome the increased threshold voltage variations and successfully drive the pull-up transistor during the subsequent write operation, thereby maintaining write reliability at reduced core voltages
Solution Approach 2:
The patent changes the voltage parameter of the bit line dynamically by applying a boosted voltage during the write operation. This parameter change allows the system to operate at reduced core voltages while maintaining sufficient write capability by temporarily increasing the bit line voltage above the normal operating level during critical write moments
2Quantity of substance
If SRAM capacity is increased as device size decreases, then storage density improves, but threshold voltage variations increase causing write failure
Solution Approach 1:
The patent compensates for threshold voltage variations caused by device scaling by dynamically changing the bit line voltage parameter. The pre-charged bit line voltage is elevated to a level that accounts for the increased threshold variations in scaled devices, ensuring sufficient overdrive voltage to overcome these variations and maintain reliable write operations in high-density SRAM arrays
3Use of energy by moving object
If write assist circuits are added to enable voltage reduction, then minimum voltage can be scaled down, but device complexity increases
Solution Approach 1:
The patent merges the write assist functionality with the existing bit line precharge circuitry. The same circuit structure serves dual purposes: normal precharging during read operations and boosted precharging during write operations. This merging approach enables voltage scaling and write assistance without adding separate dedicated write assist circuits, thereby limiting the increase in device complexity
Solution Approach 2:
The bit line precharge circuit is designed with multi-functionality to serve both read and write operations. By controlling the precharge voltage level based on the operation type, the circuit provides enhanced precharge voltage for write operations while maintaining normal precharge for read operations, eliminating the need for separate write assist circuitry and reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory layout penalties, maintains consistent voltage ratios, and improves SRAM yields, thereby reducing fabrication costs and enabling further voltage scaling without write failure, making it suitable for compiler random access memory applications.
Implementation Method 1
a distributed capacitance controlled by a write assist command to provide generation of a negative bit line voltage during the write operation
Data Source
AI summary
A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.