Negative Bitline Write Assist Driver Using Dual Capacitive Structures
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Solution Overview
Problem
Conventional negative bitline write assist (NBWA) circuits using a single voltage source for pull-down voltage often result in insufficient write assist to memory cells due to voltage variations, leading to failed writes or stability issues in memory devices.
Innovation Solution
Employing a concurrent combination of core voltage and memory voltage as the pull-down voltage for negative write assist, utilizing two capacitive structures triggered by separate voltage sources to provide a more predictable and attenuated negative boost voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage source is used for pull-down voltage in NBWA circuits, then the circuit complexity is reduced, but the write assist voltage becomes unpredictable and causes reliability issues
Solution Approach 1:
The single voltage source is segmented into two separate voltage sources (first voltage source and second voltage source), each providing voltage to separate capacitive structures. This segmentation allows independent control of voltage levels, improving reliability while maintaining manageable circuit complexity through modular architecture.
Solution Approach 2:
The invention changes the voltage parameter by using two different voltage sources with different voltage levels instead of a single voltage source. The first capacitive structure receives a first voltage and the second capacitive structure receives a second voltage, allowing the pull-down voltage to be dynamically adjusted based on operating conditions, thus improving write assist reliability.
2Reliability
If a bigger capacitive structure is added to boost the negative bitline, then the write assist capability is improved, but the power requirement and capacitive area increase
Solution Approach 1:
Instead of using one large capacitive structure, the invention segments the capacitance into two separate capacitive structures. Each capacitive structure is sized appropriately for its specific function, reducing the total capacitive area and power requirement while maintaining the necessary write assist capability through coordinated operation of both structures.
Solution Approach 2:
The invention applies partial action by using two smaller capacitive structures that each provide a portion of the required write assist effect. Rather than over-designing a single large capacitor that would consume excessive power and area, the two structures work together to provide the necessary voltage boost with optimized power and area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures a crisper edge rate at low voltages and prevents high voltage issues, maintaining a stable and effective write assist at all times, reducing reliability concerns and power requirements.
Implementation Method 1
a first capacitive structure is electrically coupled to a first voltage supply... a second capacitive structure is electrically coupled to a second voltage supply... the first capacitive structure and the second capacitive structure are capacitively coupled to a bitline
Data Source
AI summary
A memory device includes a memory cell coupled to a bitline and a bitline complement. A first capacitive structure is charged with a first voltage source such as a memory supply voltage. A second capacitive structure is charged with a second voltage source such as a core supply voltage. A coupling structure selectively and capacitively couples the first capacitive structure and the second capacitive structure to the bitline or the bitline complement, thereby applying a negative bitline write assist to the memory cell during a write operation.