Negative-Capacitance Transistor Ferroelectric Layer Thinning

Solution Overview

Problem

Current methods struggle to fabricate negative capacitance field effect transistors (NCFETs) with scaled down dimensions due to difficulties in properly forming a ferroelectric layer, especially when it is thin (e.g., between 2 and 3 nanometers) or when the transistor has a large channel width (e.g., greater than or equal to 100 nanometers).

Innovation Solution

A method involving the formation of a ferroelectric film with a thickness greater than the desired thickness, followed by annealing to achieve a crystalline state, and subsequent thinning to the desired thickness, ensures proper formation of the ferroelectric layer, regardless of transistor size. For wider channel regions, a high-K dielectric layer is used instead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a thin ferroelectric layer is used to achieve negative capacitance, then the transistor switching speed improves, but the manufacturing precision deteriorates due to difficulty in properly forming the ferroelectric layer

Engineering Contradiction:

Improveswitching speedVSAvoidferroelectric layer formation precision

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by first forming a thick ferroelectric film (greater than desired thickness) before annealing, then subsequently thinning it to the desired thickness. This reverse sequence ensures proper formation of the ferroelectric layer while achieving the required thinness for negative capacitance and fast switching.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by controlling the thickness of the ferroelectric layer through a multi-step process involving deposition of a thick film, annealing to achieve crystalline state, and then thinning to the desired thickness. This allows optimization of both manufacturing precision and switching performance.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If the transistor channel width is increased, then the ease of manufacture improves, but the manufacturing precision deteriorates due to inability to properly form ferroelectric layer

Engineering Contradiction:

Improvetransistor fabrication easeVSAvoidferroelectric layer formation precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by first forming a thick ferroelectric film before annealing, then subsequently thinning it to the desired thickness. This reverse sequence ensures proper formation of the ferroelectric layer while achieving the required thinness for negative capacitance and fast switching.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by controlling the thickness of the ferroelectric layer through a multi-step process involving deposition of a thick film, annealing to achieve crystalline state, and then thinning to the desired thickness. This allows optimization of both manufacturing precision and switching performance.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If a thick ferroelectric film is formed first, then the manufacturing precision improves, but the device complexity increases due to additional processing steps

Engineering Contradiction:

Improveferroelectric layer formation precisionVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by first forming a thick ferroelectric film before annealing, then subsequently thinning it to the desired thickness. This reverse sequence ensures proper formation of the ferroelectric layer while achieving the required thinness for negative capacitance and fast switching.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by controlling the thickness of the ferroelectric layer through a multi-step process involving deposition of a thick film, annealing to achieve crystalline state, and then thinning to the desired thickness. This allows optimization of both manufacturing precision and switching performance.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the fabrication of NCFETs with scaled down dimensions while maintaining a negative capacitance, allowing for faster switching between conducting and non-conducting states.

Implementation Method 1

annealing the ferroelectric film to have a desired phase

Methodology Applied

Scientific EffectAnnealing: Annealing

Implementation Method 2

annealing the ferroelectric film to have a desired phase

Methodology Applied

Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20250366074A1Transistor with a negative capacitance and a method of creating the same

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.