Negative Capacitance Transistor With Multilayer Ferroelectric Tuning
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Solution Overview
Problem
Existing negative capacitance devices face challenges in achieving desired capacitance values due to constraints in capacitance matching windows with single-layer ferroelectric structures, limiting their performance and flexibility in tuning capacitance.
Innovation Solution
A negative capacitance transistor with a multilayer ferroelectric structure or a single ferroelectric layer having a gradient doping profile, where each layer or portion has a specific material composition and dopant concentration, allowing for more versatile capacitance tuning and improved matching capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer ferroelectric structure is used, then the device structure is simple, but the capacitance matching flexibility is limited
Solution Approach 1:
The patent divides the single-layer ferroelectric structure into multiple layers, where each layer can have different material compositions, thicknesses, and doping concentrations. This segmentation allows independent optimization of each layer's capacitance contribution, providing enhanced tuning flexibility while maintaining manageable structural complexity through modular design
Solution Approach 2:
The patent introduces an additional compositional dimension by varying material composition and doping concentration across layers, transforming the single-degree-of-freedom single-layer structure into a multi-degree-of-freedom multilayer structure. This enables capacitance tuning through multiple independent parameters including layer thickness, material composition ratios, and dopant concentrations
2Ease of manufacture
If uniform doping is used in ferroelectric layer, then the fabrication process is simple, but the capacitance matching precision is limited
Solution Approach 1:
The patent implements non-uniform doping profiles where different regions of the ferroelectric layer have different dopant concentrations. This local quality variation allows precise control of capacitance distribution across the layer, enabling better capacitance matching with reference capacitors while maintaining compatibility with standard semiconductor doping processes
Solution Approach 2:
The patent varies doping concentration as a controllable parameter across different regions and layers of the ferroelectric structure. By adjusting dopant concentration profiles, the patent achieves precise control over capacitance values, allowing fine-tuning of the matching window without requiring fundamental changes to the fabrication process
3Quantity of substance
If higher dopant concentration is used, then the capacitance value increases, but the leakage current increases
Solution Approach 1:
The patent applies different dopant concentrations to different layers and regions of the ferroelectric structure. By strategically placing highly doped regions where high capacitance is needed and lightly doped or undoped regions where leakage must be minimized, the patent achieves optimal balance between capacitance value and leakage current through spatially varying material properties
Solution Approach 2:
The patent creates a composite ferroelectric structure with multiple layers having different material compositions and doping levels. This composite approach allows the structure to exhibit both high capacitance (from heavily doped regions) and low leakage (from lightly doped regions), effectively combining the beneficial properties of different material configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer or gradient doping approach enhances capacitance matching flexibility and device performance by providing additional degrees of freedom for tuning negative capacitance, reducing leakage, and optimizing remanent polarization and coercive field characteristics.
Implementation Method 1
A negative capacitance device is provided having a gate structure including a dielectric layer, a ferroelectric structure, and a metal gate electrode
Implementation Method 2
Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure
Data Source
AI summary
A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure is disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.