Negative-Capacitance FET Dielectrics for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling down of semiconductor devices has increased power consumption and parasitic capacitance, which negatively impacts performance and efficiency.
Innovation Solution
Incorporation of negative capacitance (NC) dielectric structures in field effect transistors (FETs), specifically using NC gate dielectric layers and spacer structures to reduce parasitic capacitance and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and speed are improved, but power consumption and parasitic capacitance increase
Solution Approach 1:
The patent changes the electrical parameters of the gate dielectric by introducing negative capacitance characteristics through ferroelectric materials. This parameter change enables voltage amplification, allowing the device to operate at lower supply voltages while maintaining high switching speeds, thus resolving the contradiction between speed and power consumption
Solution Approach 2:
The patent employs composite gate dielectric structures combining ferroelectric materials with conventional dielectric layers. This composite approach leverages the negative capacitance property of ferroelectric materials to reduce power consumption while maintaining the electrical performance and speed characteristics of scaled devices
2Quantity of substance
If semiconductor devices are scaled down to increase storage capacity, then device density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent modifies the capacitance parameter of the gate dielectric to exhibit negative capacitance behavior. This parameter change effectively reduces the total parasitic capacitance in the device, enabling higher device density and storage capacity without the usual penalty of increased parasitic effects
3Ease of manufacture
If conventional dielectric materials are used in scaled devices, then manufacturing simplicity is maintained, but subthreshold swing increases and device performance deteriorates
Solution Approach 1:
The patent uses composite gate dielectric structures that integrate ferroelectric materials with conventional dielectric layers. This composite approach maintains compatibility with existing manufacturing processes while significantly improving device performance by reducing subthreshold swing and enhancing switching characteristics
Solution Approach 2:
The patent applies ferroelectric materials specifically in the gate dielectric region where negative capacitance is most beneficial, while maintaining conventional materials in other regions. This local quality approach improves device performance without requiring complete process overhaul, balancing manufacturing simplicity with performance enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of NC dielectric materials reduces subthreshold swing, increases channel on-current to off-current ratio, and lowers power consumption, enabling faster device operation with reduced supply voltage.
Implementation Method 1
Incorporation of negative capacitance (NC) dielectric structures in field effect transistors (FETs), specifically using NC gate dielectric layers and spacer structures to reduce parasitic capacitance
Implementation Method 2
The implementation of NC dielectric materials reduces subthreshold swing, increases channel on-current to off-current ratio
Data Source
AI summary
The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.