Negative Capacitance FinFET Structure for Capacitance Matching
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Solution Overview
Problem
Existing negative capacitance transistors face challenges in achieving satisfactory performance at smaller sizes due to difficulties in forming gate structures with small critical dimensions, particularly in maintaining capacitance matching and device performance.
Innovation Solution
A negative capacitance FinFET structure is developed, incorporating a negative capacitance gate stack and channel with ferroelectric or anti-ferroelectric materials, allowing for flexible adjustment of fin structure thickness for capacitance matching, and featuring a gate dielectric structure with opposing hysteresis direction to mitigate hysteresis behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to difficulties in forming gate structures with small critical dimensions
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change allows the gate to wrap around the fin structure, providing better electrostatic control at smaller dimensions while maintaining manufacturable critical dimensions for the gate pattern.
Solution Approach 2:
The patent employs composite material structures including ferroelectric materials combined with dielectric materials in the gate stack, and different semiconductor materials (e.g., SiGe) in the fin structure. These composite structures enable capacitance matching and improved device performance while maintaining fabrication feasibility at scaled dimensions.
2Reliability
If ferroelectric material thickness is adjusted for capacitance matching, then device performance is improved, but device complexity increases
Solution Approach 1:
The patent systematically varies the thickness of ferroelectric and dielectric layers in the gate stack to achieve optimal capacitance matching. By adjusting these dimensional parameters, the device achieves improved performance metrics including threshold voltage control and drive current while maintaining a manageable structural complexity through standardized layering approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by maintaining the gate-filling process window and improving the performance of transistors at smaller sizes, enabling effective power dissipation and capacitance matching.
Implementation Method 1
incorporating a negative capacitance gate stack and channel with ferroelectric or anti-ferroelectric materials
Implementation Method 2
featuring a gate dielectric structure with opposing hysteresis direction to mitigate hysteresis behavior
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a first negative capacitance material, and an isolation structure formed over the substrate. The semiconductor device structure includes a gate structure formed over the fin structure, and a source feature and a drain feature formed over the fin structure. An interface between the fin structure and the source feature is lower than a top surface of the isolation structure.