Negative-Capacitance FinFET Gate Stack for Low Subthreshold Swing
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Solution Overview
Problem
Conventional semiconductor integrated circuits face challenges in scaling down due to increased complexity and design manufacturing issues, particularly in achieving efficient and fast transistors with reduced short channel effects and leakage.
Innovation Solution
The integration of multiple ferroelectric layers in FinFETs, where a first ferroelectric layer is epitaxially formed on the fin active region and a second ferroelectric layer is in physical contact with the gate electrode, producing a hysteresis-free or substantially hysteresis-free field effect transistor (FET) with negative gate capacitance, reducing subthreshold swing and improving current ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FET scaling is pursued, then device density increases, but short channel effects and leakage increase
Solution Approach 1:
The gate dielectric layer is segmented into multiple distinct layers including a first ferroelectric layer, a second ferroelectric layer, and an interfacial layer. This segmentation allows each layer to perform specific functions: the first ferroelectric layer provides negative capacitance for enhanced switching, the second ferroelectric layer stabilizes the structure, and the interfacial layer ensures proper interface characteristics with the semiconductor fin.
Solution Approach 2:
The gate dielectric employs a composite structure combining different ferroelectric materials with distinct properties. The first ferroelectric layer (e.g., Pb(Zr,Ti)O3 or Pb1-xLaxZr1-yTiyO3) provides strong negative capacitance effect, while the second ferroelectric layer (e.g., barium strontium titanate or barium zirconate titanate) provides structural stability and complementary ferroelectric characteristics, creating a composite system that overcomes the limitations of single-material dielectrics.
2Reliability
If FinFET structure is used, then control over channel is improved, but manufacturing complexity increases
Solution Approach 1:
The gate dielectric structure extends into the vertical dimension with multiple stacked layers, allowing the gate to control the channel from multiple sides and at different depths. This multi-layer vertical architecture enhances electrostatic control over the channel region while maintaining compatibility with standard FinFET fabrication processes.
Solution Approach 2:
The invention changes the dielectric constant parameter by introducing ferroelectric materials with high dielectric constants into the gate stack. This parameter change enables stronger electric field control over the channel at lower voltages, improving channel control without requiring proportional increases in gate voltage or current.
3Speed
If faster switching is achieved, then device performance improves, but power consumption increases
Solution Approach 1:
The ferroelectric layers utilize phase transitions between different polarization states to achieve switching. The negative capacitance effect during the ferroelectric phase transition amplifies the switching signal, enabling faster transitions between on and off states. This phase transition mechanism provides intrinsic speed enhancement while the ferroelectric hysteresis loop maintains low power consumption by reducing the voltage swing required for switching.
Solution Approach 2:
The invention replaces conventional capacitive charging/discharging mechanisms with ferroelectric polarization switching. Instead of relying solely on electrical charge accumulation, the ferroelectric materials provide a mechanical-like polarization switch that can be toggled between stable states, enabling faster and more energy-efficient switching compared to traditional RC-limited RC circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster switching, reduced power consumption, and improved Ion/Ioff current ratio in transistors, addressing the limitations of conventional FETs by leveraging ferroelectric behavior for enhanced performance.
Implementation Method 1
a first ferroelectric layer is epitaxially formed on the fin active region and a second ferroelectric layer is in physical contact with the gate electrode, producing a hysteresis-free or substantially hysteresis-free field effect transistor (FET) with negative gate capacitance
Implementation Method 2
a first ferroelectric layer is epitaxially formed on the fin active region
Data Source
AI summary
Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.