Negative Capacitance Gate Stack for Sub-Threshold Swing Reduction

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Solution Overview

Problem

MOS devices face limitations in switching speed due to the 60 mV/decade sub-threshold swing limit, which restricts further scaling of operation voltage and threshold voltage, especially in FinFET and ultra-thin-body MOSFET on silicon-on-insulator devices.

Innovation Solution

A negative capacitance gate stack structure with a doped ferroelectric layer is implemented, which includes a gate dielectric layer, a doped ferroelectric material layer, and a gate electrode, allowing for improved voltage gain by tuning the capacitance of the ferroelectric layer to match the capacitance of the gate dielectric layer, thereby reducing the sub-threshold swing below 60 mV/decade.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional MOS device structure is used, then device simplicity is maintained, but switching speed is limited by 60 mV/decade sub-threshold swing

Engineering Contradiction:

Improveswitching speedVSAvoidgate stack structure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The gate stack employs a composite structure combining gate dielectric layer, doped ferroelectric material layer, and gate electrode layer. This composite material approach enables negative capacitance effect that reduces sub-threshold swing below 60 mV/decade, thereby improving switching speed while accepting increased structural complexity.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The invention changes the electrical parameters of the gate stack by introducing a doped ferroelectric material layer with specific doping concentrations (1×10^18 to 1×10^20 atoms/cm³). This parameter modification creates negative capacitance that enhances switching speed by reducing sub-threshold swing.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If gate dielectric layer thickness is increased, then capacitance matching is easier to achieve, but device area increases

Engineering Contradiction:

Improvecapacitance matching reliabilityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The invention adjusts the thickness of the doped ferroelectric material layer (5 nm to 50 nm) to achieve capacitance matching with the gate dielectric layer. By controlling this parameter, reliable capacitance matching is achieved without significantly increasing device area, as the ferroelectric layer provides high capacitance density.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of a negative capacitance gate stack structure enhances the switching speed of transistors by achieving sub-threshold swings less than 60 mV/decade, overcoming the traditional limitations and improving the performance of MOS devices.

Implementation Method 1

Methodology Applied

Scientific EffectNegative capacitance:

Data Source

PatentUS11018239B2Semiconductor device and manufacturing method thereof

Publication Date: 2021.05.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.