Negative Capacitance Switching Element for Memory Speed
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Solution Overview
Problem
The challenge is to improve the degree of integration and performance of semiconductor memory devices while maintaining low costs, particularly in achieving high operation speed and reliability.
Innovation Solution
The proposed solution involves a switching element with a negative capacitor structure, including a first and second gate dielectric layer with a ferroelectric material, and a gate electrode configuration that allows for selective negative capacitance control, enhancing the operation speed and reliability of semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional gate structures are used in semiconductor memory devices, then manufacturing simplicity is maintained, but operation speed and degree of integration are limited
Solution Approach 1:
The gate structure is divided into multiple segments: a first gate electrode, a second gate electrode, and a floating gate electrode positioned between them. This segmentation allows independent control of different gate regions, enabling the floating gate to induce negative capacitance in the second gate dielectric layer while the first gate electrode controls the channel, thereby improving operation speed without excessive complexity
Solution Approach 2:
The floating gate electrode is nested within the space between the first and second gate dielectric layers, surrounded by dielectric materials. This nested configuration allows the floating gate to effectively couple with the second gate dielectric layer to induce negative capacitance while maintaining structural integration and avoiding excessive device complexity
2Speed
If negative capacitance is introduced to improve operation speed, then turn-on speed increases, but control precision and stability become more difficult to maintain
Solution Approach 1:
The floating gate electrode acts as a feedback mechanism that senses the voltage applied to the first gate electrode and induces corresponding negative capacitance in the second gate dielectric layer. This feedback coupling ensures precise control of the threshold voltage and capacitance characteristics, maintaining stability while achieving fast turn-on speed
Solution Approach 2:
The invention changes the capacitance parameter of the second gate dielectric layer from positive to negative by applying voltage to the floating gate electrode. This parameter change enables the gate structure to achieve steeper switching characteristics and faster turn-on speed while maintaining precise control through the controlled induction of negative capacitance
3Productivity
If 3D memory cell arrangement is implemented to reduce area, then degree of integration improves, but manufacturing precision and reliability challenges increase
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional stacked arrangement with multiple gate dielectric layers and floating gate electrodes positioned between them. This dimensional change enables higher degree of integration by utilizing vertical space, while the standardized layer stacking approach maintains manufacturing precision through established deposition and etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the negative capacitor switching element in semiconductor memory devices achieves improved operation speeds and reliability, enabling faster turn-on operations and enhanced performance characteristics.
Implementation Method 1
a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance
Implementation Method 2
the fourth gate dielectric layer including a ferroelectric material having self-induced negative capacitance
Data Source
AI summary
A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.