Negative-Capacitor Comparator Front End for Wider ADC Bandwidth
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Solution Overview
Problem
In high-frequency integrated circuits, particularly in 60 GHz transceivers, the reduction in power supply voltage complicates the design of analog-to-digital converters (ADCs) due to issues like transistor mismatch, clock kick-back, and reduced bandwidth, which affect the accuracy and efficiency of signal conversion.
Innovation Solution
The proposed solution involves a layout technique where comparators are aligned to share a common active area, eliminating the need for dummy fingers and using a clock-less pre-amplifier stage to minimize clock kick-back, along with an active negative-capacitor circuit to cancel input capacitance, thereby enhancing bandwidth and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the transistor width is increased to overcome mismatching conditions, then the matching precision is improved, but the bandwidth of the ADC is reduced due to increased input capacitance
Solution Approach 1:
An active negative-capacitor circuit is introduced as an intermediary between the PGA and the comparator inputs. This circuit generates a negative capacitance that cancels the positive input capacitance of the comparators, thereby reducing the total capacitive load without requiring smaller transistor widths. The negative-capacitor circuit uses cross-coupled transistors and capacitors to create the opposing capacitance effect.
Solution Approach 2:
The invention changes the effective capacitance parameter at the comparator inputs by introducing a negative capacitance. This allows the system to maintain small transistor widths (for high bandwidth) while effectively compensating for the capacitance that would normally result from those small widths, thus improving matching precision without sacrificing speed.
2Measurement precision
If dummy transistors are added to improve transistor matching, then the matching precision is improved, but the device complexity and power dissipation increase
Solution Approach 1:
Instead of adding dummy transistors to the comparator circuit, the invention introduces an active negative-capacitor circuit as an intermediary that achieves matching improvement through capacitance cancellation. This approach avoids the complexity and power consumption associated with dummy transistor implementations.
3Use of energy by moving object
If the power supply voltage is reduced, then the power consumption is decreased, but the bandwidth and performance of the ADC are reduced
Solution Approach 1:
The invention changes the capacitive load parameter at the comparator inputs by introducing negative capacitance. This allows the system to achieve high bandwidth performance with reduced power supply voltage, as the negative-capacitor circuit compensates for the capacitance that would normally limit speed at low voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the matching of transistors, reduces clock kick-back, and increases the bandwidth of the ADC, leading to more accurate signal conversion and lower power consumption in high-speed, high-frequency applications.
Implementation Method 1
an active negative-capacitor circuit to cancel the input capacitance of comparators
Data Source
AI summary
A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.