Negative Capacitor OSFET Back Gate Bias Control
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Solution Overview
Problem
Conventional oxide semiconductor field effect transistors (OSFETs) face a trade-off between achieving ultra-low off-state current in sleep/standby mode and high operation speed in active mode, where both cannot be simultaneously optimized.
Innovation Solution
Incorporating a negative capacitor with a ferroelectric material layer and a control circuit that dynamically adjusts the back gate bias of the OSFET, allowing for reduced off-state current in sleep mode and enhanced operation speed in active mode, while also compensating for parasite capacitance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional OSFET structure is used, then ultra low off-state current is achieved, but operation speed is reduced
Solution Approach 1:
The patent applies dynamics by making the back gate bias dynamically adjustable through a control circuit that can switch between different voltage levels. This allows the transistor to transition between different operating states (high off-state current for speed vs. low off-state current for power savings), resolving the contradiction between speed and power consumption by enabling adaptive operation modes.
Solution Approach 2:
The patent changes the electrical parameter (back gate bias voltage) to simultaneously optimize both off-state current and operation speed. By applying different back gate biases, the transistor can operate in different regimes: one optimized for low off-state current and another for high operation speed, thus resolving the contradiction through parameter variation.
2Speed
If back gate bias is increased to improve operation speed, then operation speed is improved, but off-state current increases
Solution Approach 1:
The control circuit dynamically adjusts the back gate bias based on operational requirements. During active mode, the bias is set to improve operation speed; during sleep/standby mode, the bias is adjusted to minimize off-state current. This dynamic adjustment resolves the contradiction by allowing both conditions to be optimized at different times.
Solution Approach 2:
The system employs periodic switching between different back gate bias states corresponding to active and sleep modes. This periodic action allows the transistor to alternate between high-speed operation and low-power state, achieving both high operation speed when needed and low off-state current during idle periods.
3Device complexity
If multiple components are integrated on the same level, then device integration is improved, but interference between components increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by disposing the control circuit at a different horizontal level (above or below) the field effect transistor and negative capacitor. This dimensional change allows high integration while minimizing electromagnetic interference and parasitic effects between components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration balances operation speed in active mode with reduced off-state current in sleep mode, lowers power consumption, and improves manufacturing process control by minimizing interference between components.
Implementation Method 1
the negative capacitor includes a pair of electrodes and a ferroelectric material layer disposed between the pair of electrodes
Data Source
AI summary
A semiconductor device and an integrated circuit are provided. The semiconductor device includes a field effect transistor, a negative capacitor and a control circuit, which are disposed at different horizontal levels on a substrate. The field effect transistor includes a front gate, a back gate and an oxide semiconductor layer disposed between the front gate and the back gate. The negative capacitor is electrically connected to the back gate of the field effect transistor. The negative capacitor includes a pair of electrodes and a ferroelectric material layer disposed between the pair of electrodes. The negative capacitor is electrically connected between the back gate of the field effect transistor and the control circuit, the control circuit is configured to charge the negative capacitor and to asses a voltage between the pair of electrodes of the negative capacitor.