Fixed Negative Charge Plug for Faster Memory Erase
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Solution Overview
Problem
Current memory devices face challenges in efficiently performing erase operations due to the difficulty in discharging electrons trapped in charge trap layers, which affects data retention and storage efficiency.
Innovation Solution
Incorporating a plug with a material layer having a fixed negative charge within the vertical hole of the memory device's stack structure, allowing for easier discharge of electrons during the erase operation by creating a positive charge in the channel layer that can move adjacent to the memory layer, facilitating the removal of trapped electrons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional memory device structure without a fixed negative charge plug is used, then the device structure is simpler, but the erase operation efficiency is poor due to difficulty in discharging trapped electrons
Solution Approach 1:
The patent applies preliminary action by pre-forming a plug with fixed negative charge in the vertical hole before forming the channel layer and memory layer. This pre-positioned negative charge creates a positive charge region in the channel layer during erase operations, which actively attracts and discharges trapped electrons from the charge trap layer, thereby improving erase operation efficiency without requiring additional erase mechanisms.
Solution Approach 2:
The plug with fixed negative charge acts as an intermediary element between the control gate and the channel layer. It mediates the charge discharge process by generating a positive charge region in the channel layer that facilitates electron removal from the charge trap layer, enabling efficient erase operations without direct intervention from external erase circuits.
2Productivity
If electrons in the charge trap layer are difficult to discharge, then data retention is maintained, but erase operation efficiency deteriorates
Solution Approach 1:
The patent changes the electrical parameter distribution by introducing a plug with fixed negative charge, which fundamentally alters the charge distribution in the vertical hole structure. This parameter change enables dynamic creation of positive charge regions in the channel layer during erase operations, facilitating electron discharge while maintaining data retention during normal operation through the stable fixed negative charge in the plug.
3Productivity
If a plug with fixed negative charge material layer is added, then electron discharge during erase operation is facilitated, but the manufacturing process becomes more complex
Solution Approach 1:
The plug with fixed negative charge is formed in advance during the manufacturing process, before the channel layer and memory layer are deposited. This preliminary formation integrates the erase enhancement feature into the base fabrication sequence, avoiding the need for additional post-processing steps or complex manufacturing modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the erase operation efficiency by allowing for the easy discharge of electrons from the charge trap layer, thereby improving data retention and storage efficiency in memory devices.
Implementation Method 1
the plug includes a material layer having a fixed negative charge
Implementation Method 2
creating a positive charge in the channel layer that can move adjacent to the memory layer
Data Source
AI summary
The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.