Regulated Negative Charge Pump for MRAM Read Margin Stability
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Solution Overview
Problem
In MRAM devices, parasitic currents can mask the desired read-current, making it difficult to distinguish between logic '0' and '1' states, especially at high temperatures and in large memory arrays.
Innovation Solution
The implementation of negative charge pump circuits and a compensation circuit to generate a stable negative voltage, which is applied to the gates of access devices in MRAM bit-cells, minimizing parasitic currents and ensuring proper read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read operations are used in MRAM, then read-current flows through the MTJ, but parasitic current from unselected bit-cells masks the desired read-current, making it difficult to distinguish between logic states
Solution Approach 1:
The patent applies preliminary anti-action by generating a compensation current that is equal in magnitude but opposite in direction to the parasitic current before the read operation completes. This compensation current is injected into the unselected bit-cell to cancel out the parasitic current, thereby preventing it from masking the desired read-current and preserving the read margin for accurate logic state detection.
Solution Approach 2:
The patent introduces an intermediary compensation current as a mediator between the parasitic current and the desired read-current. This compensation current acts as a counterbalancing force that neutralizes the harmful parasitic current, allowing the read operation to proceed accurately without interference from unselected bit-cells.
2Quantity of substance
If memory array size increases, then storage capacity improves, but parasitic current from additional unselected bit-cells increases, reducing read margin
Solution Approach 1:
The patent implements feedback by continuously monitoring the parasitic current generated by unselected bit-cells and dynamically adjusting the compensation current accordingly. The compensation circuit responds to changes in parasitic current magnitude (which increases with array size) by providing an equal and opposite compensation current, thereby maintaining stable read margin regardless of memory array expansion.
3Temperature
If temperature increases, then device operation continues, but parasitic current increases and masks the read-current, causing read failures
Solution Approach 1:
The patent applies preliminary anti-action by generating a compensation current that anticipates and counteracts the temperature-induced increase in parasitic current. As temperature rises and parasitic current increases, the compensation circuit detects this change and provides an opposing compensation current, thereby preventing read failures even at elevated temperatures where parasitic current would otherwise mask the desired read-current.
Data Source
AI summary
In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.