Negative Gate Stress for NAND Flash Memory Programming
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Solution Overview
Problem
In NAND Flash memory devices, multi-pass programming faces challenges with degraded programming distributions due to shallowly-trapped charges, leading to increased read window budget reduction and high power consumption, especially when negative gate stress operations are applied after verify operations.
Innovation Solution
A novel negative gate stress scheme is implemented, enabling NGS operations on both selected and unselected rows of memory cells during non-last programming passes to remove shallowly-trapped charges, thereby narrowing threshold voltage distributions and maintaining read window budget without decreasing it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If negative gate stress operation is applied after verify operation in multi-pass programming, then shallowly-trapped charges are removed, but power consumption increases
Solution Approach 1:
The patent applies NGS operation between the programming operation and verify operation as a preliminary action to remove shallowly-trapped charges before verification. This prevents charge loss that would occur if NGS were applied after verify, thereby reducing the need for re-programming and lowering overall power consumption while maintaining programming distribution precision.
Solution Approach 2:
The patent maintains continuous useful action by performing NGS operation in the idle time between programming and verify operations. This ensures that charge trapping is continuously managed without interrupting the programming flow, improving programming distribution while avoiding additional power consumption from separate correction cycles.
2Manufacturing precision
If NGS operation is performed on selected row only, then programming operation is simple, but threshold voltage distribution narrows less effectively
Solution Approach 1:
The patent merges the NGS operation for the selected row with NGS operation for the unselected row by applying negative voltage to both word lines simultaneously. This combined approach narrows threshold voltage distributions more effectively for both rows while maintaining a simple programming operation structure that can be implemented with existing circuitry.
3Manufacturing precision
If NGS operation is applied to unselected row, then threshold voltage distribution narrows for both selected and unselected rows, but programming operation complexity increases
Solution Approach 1:
The patent makes the programming operation universal by designing the NGS circuit to handle both selected and unselected rows through the same control mechanism. The word line driver can apply negative voltage to any combination of word lines, making the operation multi-functional without requiring separate dedicated circuits for each row type, thus narrowing distributions effectively while controlling complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively narrows the threshold voltage distributions and maintains the read window budget, reducing power consumption by applying NGS operations in a non-last programming pass, ensuring efficient data retention and reading operations.
Implementation Method 1
perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation
Data Source
AI summary
A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.