Negative-Voltage I/O ESD Circuit Without Parasitic Diode Leakage
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Solution Overview
Problem
Conventional ESD protection circuits for I/O pins with negative voltage suffer from parasitic diode formation, leading to junction forward leakage current, which increases manufacturing costs due to the need for deep N-well isolation techniques.
Innovation Solution
An ESD protection circuit comprising a P-type device and a diode, where the P-type device is directly connected between the I/O pin and ground voltage, and the anode of the diode is connected to the I/O pin without any N-type doping/diffusion connection, eliminating the need for deep N-well isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If deep N-well isolation technique is used to isolate P-type diffusion and N-type diffusion, then parasitic diode formation is prevented, but manufacturing cost increases
Solution Approach 1:
The patent extracts the problematic N-type diffusion connection from the I/O pin structure. By configuring the ESD protection circuit so that no N-type doping/diffusion is directly connected to the I/O pin, the design eliminates the source of parasitic diode formation without requiring additional isolation structures, thereby avoiding increased manufacturing costs
Solution Approach 2:
Instead of adding isolation structures to prevent parasitic diodes (conventional approach), the patent inverts the approach by carefully designing the ESD protection circuit topology where the diode anode connects to the I/O pin while ensuring no N-type diffusion directly touches the I/O pin, thus preventing parasitic diode formation through structural inversion rather than isolation
2Reliability
If conventional ESD protection circuit with diodes is used for negative voltage I/O pin, then ESD protection is provided, but junction forward leakage current is generated
Solution Approach 1:
The patent applies local quality by creating different doping type connections at different locations. Specifically, the I/O pin is connected to P-type diffusion for the ESD protection diode, while N-type diffusion is kept isolated from the I/O pin. This localized differentiation of doping types allows the circuit to provide ESD protection through the P-type diode while preventing the formation of parasitic N-P junctions that would cause forward leakage current during negative voltage operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents junction forward leakage current, reduces power consumption, and avoids the increased manufacturing costs associated with deep N-well processes, while effectively protecting against ESD strikes.
Implementation Method 1
these diodes absorb the short-duration voltage pulses during the ESD strike, that is high peak currents from the ESD strike flow to the ground through the diodes and limit the ESD strike voltages from damaging the internal circuits
Implementation Method 2
a parasitic diode may be formed between the I/O pin and the ground voltage so that a junction forward leakage current is generated
Data Source
AI summary
The present invention provides a chip including an I/O pin and an ESD protection circuit. The ESD protection circuit includes a P-type device and a first diode, wherein the P-type device is coupled between the I/O pin and a ground voltage, and an anode of the first diode is directly connected to the I/O pin. In addition, the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.