Negative-Voltage Level Shifter With Medium-Voltage Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to ensure stable operation of negative-voltage level shifters in semiconductor devices, particularly when the low power-supply voltage VDD is lowered due to downsizing, as they struggle to function when the negative high-voltage power supply is inactive, leading to issues with breakdown-voltage relaxation and increased resistance in the current path.
Innovation Solution
A semiconductor device is designed with a negative-voltage level shifter that includes a first level shifter converting a high input signal from a first power-supply voltage to a medium voltage and a second level shifter converting a low output signal to a negative high voltage, allowing stable operation even when the voltage value of the input signal is lowered, using a VDD-VBIAS level shifter and a medium-voltage generating circuit to manage power-supply voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the low power-supply voltage VDD is lowered due to downsizing, then the size of the logic circuit is reduced, but the negative-voltage level shifter becomes difficult to operate when the negative high-voltage power supply is inactive
Solution Approach 1:
A medium-voltage generating circuit is introduced as an intermediary component between the low-voltage logic circuit and the negative-voltage level shifter. This circuit generates a medium voltage (e.g., 2.5V) from the low power-supply voltage VDD (e.g., 1.0V), providing sufficient voltage headroom for the negative-voltage level shifter to operate reliably even when the negative high-voltage power supply is inactive, thus resolving the contradiction between downsizing and operational reliability
Solution Approach 2:
The patent changes the voltage parameter supplied to the negative-voltage level shifter from the low power-supply voltage VDD to a medium voltage generated by the medium-voltage generating circuit. This parameter change ensures that the voltage supplied is always sufficient (e.g., 2.5V) to maintain proper operation of the negative-voltage level shifter, regardless of how low VDD is lowered for downsizing purposes
2Reliability
If VDD is used as the positive voltage for the negative-voltage level shifter to achieve breakdown-voltage relaxation, then breakdown-voltage issues are mitigated, but the level shifter cannot operate when VDD is excessively lowered
Solution Approach 1:
The medium-voltage generating circuit acts as a mediator that decouples the relationship between VDD and the negative-voltage level shifter. It converts the excessively lowered VDD into a sufficient medium voltage, allowing the level shifter to operate reliably while the low VDD still provides breakdown-voltage relaxation for the logic circuit, thus resolving both concerns simultaneously
Solution Approach 2:
The voltage supply system is segmented into multiple stages: the low-voltage VDD supplies the logic circuit with breakdown-voltage relaxation, while the medium-voltage generating circuit creates a separate medium voltage supply for the negative-voltage level shifter. This segmentation allows each component to receive the appropriate voltage level for its specific requirements
Data Source
Figure 1
Figure 2
Figure 3(A)~3(D)
AI summary
To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.