Negative Voltage Level Shifter Circuit for Fast Capacitive Loads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional negative voltage level shifter circuits face issues with poorly driven output nodes, slow circuit behavior due to capacitive load, and reliability problems caused by voltage stress and unbalanced load capacitance, especially when dealing with high negative supply voltages.
Innovation Solution
A negative voltage level shifter circuit design that uses a pair of input transistors, a cascode sub-circuit, and cross-coupled transistors driven by comparator sub-circuits to ensure well-driven output voltages and minimize voltage stress, requiring fewer supply voltages and maintaining high speed even with high capacitive loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional negative voltage level shifter circuits are used, then the circuit can shift voltage levels, but the output nodes are poorly driven and the circuit becomes slow when driving capacitive load
Solution Approach 1:
The circuit is divided into multiple functional stages: input transistors (MP1, MP2), cascode stages (MP3-MP4, MN1-MN2), cross-coupled transistors (MN3-MN4, MP5-MP6), and output transistors (MN5-MN6, MP7-MP8). Each stage is optimized for specific functions, with output transistors specifically designed to strongly drive the output nodes, resolving the contradiction between speed and driving capability.
Solution Approach 2:
The patent combines multiple functions into integrated sub-circuits: the cascode sub-circuit merges impedance transformation and voltage level shifting, while the cross-coupled transistors merge state locking and output driving functions. This integration improves overall circuit efficiency and output drive strength without sacrificing speed.
2Adaptability or versatility
If the negative supply voltage VNEG is made more negative to expand voltage range, then the voltage level shifting range increases, but transistor voltage stress increases causing reliability issues
Solution Approach 1:
The cascode transistors (MP3, MP4, MN1, MN2) act as intermediary devices between the input transistors and output transistors. They distribute and isolate voltage stresses, allowing the circuit to handle more negative VNEG voltages without subjecting individual transistors to excessive stress, thus expanding the voltage range while maintaining reliability.
Solution Approach 2:
The patent changes the voltage parameters at different circuit nodes through the cascode stages. The cascode transistors create intermediate voltage levels that progressively transform the voltage from the input stage to the output stage, reducing peak voltage stress on any single transistor while achieving the full voltage range expansion.
3Reliability
If cross-coupled PMOS transistors are added to force output nodes to full GCASC level, then the output voltage level stability improves, but the circuit complexity increases
Solution Approach 1:
The cross-coupled PMOS transistors (MP5, MP6) are designed to perform multiple functions: they lock the output nodes to full GCASC level, provide strong driving capability for capacitive loads, and maintain circuit symmetry. This multi-functionality achieves voltage stability without proportionally increasing circuit complexity.
4Device complexity
If output nodes are taken directly from the basic circuit structure, then the circuit simplicity is maintained, but the output signals are not well driven and vary with threshold voltage
Solution Approach 1:
The output transistors (MN5-MN6, MP7-MP8) are prepared in advance with optimal sizing and configuration to provide strong driving capability. The cross-coupled transistors (MN3-MN4, MP5-MP6) are configured beforehand to lock the output nodes to stable voltage levels (GCASC and VNEG), ensuring that when the circuit operates, the output nodes are already positioned at stable potentials that are insensitive to threshold voltage variations.
Data Source
AI summary
A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.