Negative-Voltage Level Shifter Using Medium-Voltage Conversion
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Solution Overview
Problem
The downsizing of logic circuits in semiconductor devices leads to a reduction in low power-supply voltage, making it difficult for negative-voltage level shifters to operate when the negative high-voltage power supply is inactive, as the threshold voltage of high breakdown-voltage MOS transistors is not lowered, resulting in inadequate voltage margins and operational issues.
Innovation Solution
A semiconductor device with a negative-voltage level shifter configuration that includes a first level shifter converting a high input signal to a medium voltage and a second level shifter converting the output signal to a negative high voltage, using a medium voltage between the first and second power-supply voltages, allowing stable operation even with lowered input signal voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the low power-supply voltage VDD is lowered due to logic circuit downsizing, then the logic circuit size is reduced, but the negative-voltage level shifter cannot operate properly when the negative high-voltage power supply is inactive
Solution Approach 1:
The patent introduces a medium-voltage power supply (VCC) as an intermediary between the low power-supply voltage (VDD) and the negative high voltage (VEE). The level shifter uses this medium voltage to provide adequate voltage margins for proper operation, especially when the negative high-voltage power supply is inactive. This intermediary voltage supply resolves the contradiction by enabling level shifter operation at lower VDD values without compromising reliability.
2Productivity
If the low power-supply voltage VDD is lowered, then scaling efficiency is improved, but the voltage margin for high breakdown-voltage MOS transistors becomes insufficient
Solution Approach 1:
The patent changes the voltage parameter configuration by introducing a medium-voltage power supply (VCC) that operates at a higher voltage level than VDD. This parameter change allows the level shifter to maintain adequate voltage margins across the transistor stack even when VDD is lowered for scaling, thus improving scaling efficiency without sacrificing voltage margin strength.
3Device complexity
If conventional level shifter configuration is used with lowered VDD, then device complexity is reduced, but operational functionality is lost when VEE is inactive
Solution Approach 1:
The patent enhances the universality of the level shifter by making it capable of operating in multiple modes: when the negative high-voltage power supply (VEE) is active and when it is inactive. The medium-voltage power supply (VCC) enables the level shifter to function properly in both scenarios, providing operational adaptability without significantly increasing device complexity.
Data Source
AI summary
To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.