Negative Level Shifter for Nonvolatile Memory Reliability
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently shifting voltage levels for enabling and disabling operations due to limitations in existing level shifter technologies, which affect the reliability and performance of memory cell operations.
Innovation Solution
A negative level shifter is introduced, utilizing a combination of low voltage and high voltage transistors with different characteristics to shift input signals to complementary output levels, and a latch circuit to drive these outputs based on voltage levels, enabling reliable switching between power supply and negative voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing level shifter technologies are used, then the device complexity is reduced, but the reliability margin and operational performance deteriorate
Solution Approach 1:
The level shifter is divided into multiple functional blocks: a first level shifter for initial voltage level conversion, a latch circuit for signal latching and level shifting, and a second level shifter for final voltage level conversion. This segmentation allows each block to be optimized for specific functions, improving overall reliability while managing complexity through modular design.
Solution Approach 2:
The latch circuit acts as an intermediary between the first and second level shifters. It receives signals from the first level shifter, latches them, performs level shifting, and outputs to the second level shifter. This intermediary structure ensures proper signal level translation and timing control, enhancing reliability in multi-voltage environments.
2Manufacturing precision
If existing level shifter technologies are used, then the device structure is simplified, but the switching accuracy and operational performance deteriorate
Solution Approach 1:
The circuit uses dynamic control signals (enable signal and inverted enable signal) to control the switching of transistors in the latch circuit and level shifters. This dynamic operation allows precise control of signal levels and timing, ensuring accurate switching between different voltage states while adapting to operational requirements.
Solution Approach 2:
The circuit changes voltage parameters at different stages: the first level shifter converts input voltage levels, the latch circuit latches and shifts levels, and the second level shifter converts to final output levels. These parameter changes ensure accurate signal level translation matching specific voltage requirements of memory cell operations.
3Productivity
If simple switching circuits are used, then the device complexity is reduced, but the operational performance and reliability in multi-voltage environments deteriorate
Solution Approach 1:
The level shifter circuit performs multiple functions: voltage level conversion, signal latching, timing control, and level shifting. This multi-functionality ensures reliable operation in multi-voltage environments by handling various signal conditions within a single integrated circuit structure, improving operational performance without requiring multiple separate circuits.
Data Source
AI summary
A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.