Negative Voltage Level Shifter Using Symmetric NMOS Paths
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Solution Overview
Problem
Existing negative voltage level shifters in low voltage circuits face challenges with safe operating area violations and increased circuit complexity, power consumption, and area due to the use of asymmetric high voltage transistors or static bias circuits.
Innovation Solution
A level shifter circuit utilizing symmetric low voltage NMOS transistors with a specific input path configuration that avoids safe operating area violations, implemented with symmetric low voltage CMOS devices, including a first input path coupling an input node to a gate of a first NMOS transistor and a second input path through an inverter, ensuring all transistors operate within their safe operating areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asymmetric high voltage transistors (LDMOSFETs) are used to avoid SOA violations, then device reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent applies asymmetry in the circuit topology rather than in individual transistor structures. The level shifter uses asymmetric signal paths: one path handles the high-to-low transition while another handles low-to-high transition, allowing symmetric transistors to operate within their SOA by distributing voltage stress across different operational phases
Solution Approach 2:
The level shifter circuit is segmented into multiple transistor stages working in sequence. The input stage transistors handle initial signal conditioning, while output stage transistors handle the level conversion, dividing the voltage stress across multiple devices rather than requiring a single high-voltage transistor
2Reliability
If static bias circuits are added to prevent SOA violations, then device reliability is improved, but power consumption increases
Solution Approach 1:
The circuit employs periodic switching of transistor pairs to handle voltage level transitions. During operation, transistors are alternately activated and deactivated in a periodic manner, allowing each transistor to remain within its SOA during its active phase while reducing overall power consumption compared to continuously biased circuits
Solution Approach 2:
The bias conditions of the transistors are made dynamic rather than static. The circuit adjusts transistor operating points based on the input signal state, allowing transistors to operate at optimal points during different phases of operation without requiring continuous static bias current
3Use of energy by moving object
If low voltage transistors are used for reduced power consumption, then power efficiency is improved, but safe operating area violations occur
Solution Approach 1:
The circuit changes operating parameters dynamically to keep transistors within their SOA. By adjusting gate voltages and source/drain connections based on the operational phase, the circuit allows low-voltage transistors to handle higher instantaneous voltages without permanent damage, maintaining both low power consumption and reliability
4Reliability
If design modifications are made to avoid SOA violations, then device reliability is improved, but circuit area increases
Solution Approach 1:
The level shifter circuit uses universal low-voltage transistor cells that perform multiple functions. The same transistor structure is used in different stages and configurations to handle both input buffering and output driving, eliminating the need for separate high-voltage transistor structures and reducing overall circuit area
Data Source
AI summary
A negative voltage level shifter. A circuit is provided that includes a first input path that couples an input node to a gate of a first n-type metal-oxide semiconductor (NMOS) transistor, wherein the first NMOS transistor has a drain coupled to a zero volt supply and a source coupled to a gate of a second NMOS transistor, wherein the second NMOS transistor incudes a source coupled to a negative power supply of −V volts and a drain coupled to an output node; and a second input path that couples the input node to a gate of a third NMOS transistor via an inverter, wherein the third NMOS transistor has a drain coupled to the zero volt supply and a source coupled to the output node.