Negative Level-Shifter Circuit That Switches When VNEG Reaches Zero
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Solution Overview
Problem
Existing level-shifter circuits lose switching ability when the negative polarization voltage reaches zero, causing transistor stress and functionality issues in low-voltage devices interfacing with high-voltage components, particularly in flash memory cells.
Innovation Solution
A level-shifter circuit design that includes a cascode stage with PMOS and NMOS transistors, a latch stage, and additional transistors to manage voltage dynamics between VDD and zero, ensuring transistors are not under stress and maintaining switching capability even when VNEG falls to zero, with variants addressing overdrive and switching time issues through boost mechanisms and decoupling of high and low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a negative-level shifter is used to shift low-voltage control signals to negative high voltages, then the ability to interface with high-voltage components is improved, but the transistors are polarized in stress conditions by the channel oxide and lose switching ability when VNEG becomes zero
Solution Approach 1:
The level shifter is divided into two independent stages: a first stage that generates the negative voltage signal and a second stage that transfers it to the output. This segmentation allows each stage to be optimized independently, with the first stage handling voltage generation and the second stage handling signal transfer, thereby maintaining switching capability even when VNEG reaches zero.
Solution Approach 2:
A latch circuit is introduced as an intermediary element between the input and output stages. The latch circuit maintains the output signal state even when the negative voltage becomes zero, acting as a buffer that decouples the switching function from the voltage level, thus preserving reliability.
2Power
If transistors are used in negative-level shifters with high negative voltages, then the ability to drive high-voltage loads is improved, but the channel oxide experiences stress conditions leading to device degradation
Solution Approach 1:
The circuit is segmented into voltage generation and signal transfer functions. The first stage handles the high-voltage generation while the second stage transfers the signal without exposing transistors to continuous stress, reducing cumulative damage to the channel oxide.
Solution Approach 2:
The latch circuit is prepared in advance to capture and hold the signal state before the negative voltage reaches zero. This preliminary action prevents the transistors from experiencing stress conditions during the voltage transition, thereby protecting the channel oxide.
3Productivity
If the negative voltage VNEG is increased to improve switching performance, then the switching capability is enhanced, but the transistor stress and potential loss of functionality increases
Solution Approach 1:
By separating voltage generation from signal transfer, the system can optimize VNEG for switching performance in the first stage while the second stage ensures reliable output regardless of VNEG level, including when it reaches zero.
Solution Approach 2:
The latch circuit provides feedback to maintain the output state based on the input signal, ensuring that switching performance is maintained even when VNEG varies or reaches zero, thereby decoupling productivity from reliability concerns.
Data Source
AI summary
A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level.