Negative Oxide Layer for CMOS Image Sensor Dark Current Reduction
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Solution Overview
Problem
CMOS image sensors face challenges in reducing excessive leakage current, known as dark current, which leads to 'white pixel' defects due to mechanical and electrical stress during fabrication, affecting sensitivity and noise levels, and traditional methods like ion implantation for forming a P+ layer either damage the light sensing region or fail to adequately reduce dark current.
Innovation Solution
A semiconductor device with a negative oxide layer is introduced, which is formed over the light sensing region to suppress and eliminate dark current by attracting and accumulating holes, thereby reducing electron generation and leakage current, without damaging the region like ion implantation does, and can be processed at low temperatures to maintain photoelectric conversion characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to form a P+ layer to reduce dark current, then leakage current is reduced, but the light sensing region is damaged
Solution Approach 1:
An intrinsic semiconductor layer is introduced as an intermediary between the P+ layer and the light sensing region. This intermediate layer acts as a buffer that prevents direct damage to the light sensing region while still allowing the P+ layer to effectively reduce dark current through charge carrier generation
Solution Approach 2:
The patent applies different doping concentrations at different locations: a heavily doped P+ layer for dark current reduction, an intrinsic layer for protection, and lightly doped regions in the light sensing area. This localized differentiation allows each region to perform its specific function optimally
2Reliability
If high temperature annealing is used to activate dopants, then dopant activation is improved, but photoelectric conversion characteristics deteriorate
Solution Approach 1:
The patent changes the temperature parameter from high temperature annealing to low temperature processing. By using low temperature plasma treatment, dopants are activated without subjecting the light sensing region to high thermal stress, thereby preserving photoelectric conversion characteristics
Solution Approach 2:
Thermal annealing is replaced with plasma treatment. Instead of using heat to activate dopants, the patent uses plasma chemistry to achieve dopant activation at low temperatures, substituting a thermal process with a chemical/plasma-based process
3Reliability
If the P+ layer is formed to reduce dark current, then leakage current is suppressed, but the light sensing region is damaged by ion implantation
Solution Approach 1:
The intrinsic semiconductor layer serves as a protective intermediary that absorbs the mechanical damage from ion implantation while allowing the electrical function of dark current reduction to proceed. This layer acts as a buffer zone that protects the sensitive light sensing region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The negative oxide layer effectively reduces leakage current and improves the performance of white pixels by enhancing isolation and reducing interfacial defects, while avoiding the damage and thermal issues associated with traditional high-temperature annealing processes.
Implementation Method 1
A semiconductor device with a negative oxide layer is introduced, which is formed over the light sensing region to suppress and eliminate dark current by attracting and accumulating holes
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a light sensing feature, a negative oxide layer, a gate dielectric layer and a transfer gate. The light sensing feature is configured in the substrate to detect an incoming radiation. The negative oxide layer is over the light sensing feature. The gate dielectric layer is over the negative oxide layer. The transfer gate is over the gate dielectric layer.