Negative-Slope Gate Cavity for Lower RF Switch Capacitance
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Solution Overview
Problem
In semiconductor devices, particularly RF switches, there is a challenge in simultaneously minimizing on-resistance (Ron) and off-state capacitance (Coff), as conventional manufacturing processes tend to increase one parameter at the expense of the other.
Innovation Solution
The introduction of a cavity, such as an air gap, with a negative sloped sidewall in the dielectric layer over a transistor gate, which helps in reducing Coff by controlling the effective dielectric constant and improving RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a cavity with negative sloped sidewall is introduced in the dielectric layer over the gate, then off-state capacitance is reduced, but device complexity increases
Solution Approach 1:
The cavity sidewall is formed with a negative slope angle rather than a vertical or positive slope, creating a curved or angled interface between the cavity and dielectric layer. This geometric curvature optimizes the electric field distribution, reducing capacitance between the gate and overlying conductors while maintaining manufacturing feasibility through controlled etching processes.
Solution Approach 2:
The invention transitions from a simple planar or vertically-sided cavity to a three-dimensional cavity with negative sloped sidewalls. This dimensional modification of the cavity geometry creates additional space optimization and electric field control in the vertical dimension, reducing capacitance without requiring larger lateral dimensions that would increase device area.
Data Source
AI summary
A semiconductor device includes a transistor including a gate and a dielectric layer over the gate. A cavity is in the dielectric layer above the gate and a portion of the cavity over the gate has a negative sloped sidewall in the dielectric layer. The negative sloped sidewall provides a portion of the cavity having a trapezoidal cross-section having a first width at a lower end adjacent the gate and a second width smaller than the first width at an upper end. The negative sloped sidewall thus places a wider portion of the cavity closer to the gate, which decreases gate-contact capacitance.