Negative-Threshold NAND Flash for High-Bandwidth Low-Power Reads
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Solution Overview
Problem
Conventional NAND memory devices suffer from low bandwidth and high power consumption, making them unsuitable alternatives to high bandwidth memory (HBM) devices, particularly in applications requiring rapid data access and low power consumption, such as large language models.
Innovation Solution
Implementing a high bandwidth flash (HBF) package with a one bit per memory cell (SLC) storage scheme, where memory cells have threshold voltages less than zero Volts, and using read pass voltages of zero Volts to improve read performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional NAND memory devices are used, then cost is reduced compared to DRAM, but bandwidth is too low and power consumption is too high to be a viable alternative to HBM
Solution Approach 1:
The patent changes the voltage parameters of the memory system by introducing negative threshold voltage memory cells and using negative read pass voltages (e.g., -1V to 0V) instead of conventional positive voltages. This parameter change enables both low-power operation and high-speed read access, simultaneously addressing the contradiction between power consumption and bandwidth by allowing frequent reads without excessive power usage.
2Productivity
If read pass voltage is applied to unselected word lines, then read operation is enabled, but voltage ramping between read operations consumes power and reduces performance
Solution Approach 1:
The patent applies equipotentiality by setting the read pass voltage to a negative value (e.g., -1V to 0V) that matches the threshold voltage state of unprogrammed memory cells. This allows unselected word lines to remain at a stable negative potential between read operations, eliminating the need for voltage ramping and reducing both power consumption and access time while maintaining read performance.
3Productivity
If both erased and programmed data states have threshold voltages less than 0V, then read performance is improved and power consumption is reduced, but requires specialized voltage control circuitry
Solution Approach 1:
The patent implements universality by designing the voltage control circuitry to generate a single negative read pass voltage that serves multiple functions: it acts as the read voltage for selected word lines, the pass voltage for unselected word lines, and the reference potential for threshold voltage comparison. This multi-functional approach reduces circuit complexity despite the specialized negative voltage requirement.
Data Source
AI summary
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state. The memory cells in both the erased data state and in the programmed data state have threshold voltages Vt that are less than 0 V.