Negative Well Voltage Biasing for NAND Flash Program Disturb
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Solution Overview
Problem
NAND flash memory devices experience program disturb due to parasitic capacitance coupling, leading to increased susceptibility of neighboring cells to over-programming as the number of program/erase cycles increases, and existing methods to mitigate this issue, such as increasing Vpass voltage, can worsen the condition.
Innovation Solution
The solution involves biasing unselected word lines with a negative voltage before transitioning to Vpass, coupled with a positive well voltage, creating a larger voltage swing on the source and drain regions of unselected cells, thereby reducing program disturb without increasing Vpass voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Vpass voltage is increased to reduce program disturb on unselected cells, then program disturb is reduced, but source and drain regions of uninhibited bit line cells are coupled to higher voltage, worsening program disturb on those cells
Solution Approach 1:
The patent applies different voltage conditions to different groups of cells based on their bit line state. Inhibited bit line cells receive protection through negative well voltage, while uninhibited bit line cells maintain their source/drain coupling to 0V. This localized differentiation resolves the contradiction by protecting only the cells that need protection without adversely affecting other cells.
Solution Approach 2:
The patent introduces a negative well voltage as an intermediary protective mechanism. Instead of directly manipulating Vpass voltage to protect unselected cells, the negative well voltage acts as an intermediate layer that repels electrons from the channel of unselected cells, preventing program disturb without affecting the source/drain coupling of uninhibited bit line cells.
2Productivity
If the number of program/erase cycles increases, then memory capacity and usage increase, but voltage difference between programmed and erased states narrows, making cells more susceptible to over-programming
Solution Approach 1:
The patent applies negative well voltage to unselected cells before programming operations begin. This preemptive measure creates a protective potential barrier that cushions unselected cells against the narrowing voltage differences that occur after multiple program/erase cycles, preventing over-programming even as memory undergoes extensive use.
3Quantity of substance
If parasitic capacitance coupling between selected word line and adjacent word lines is present, then memory cell density is maintained, but neighboring cells experience program disturb
Solution Approach 1:
The patent extracts the protective mechanism from the Vpass voltage system and applies it separately through the well voltage system. By taking out the protection function and implementing it through negative well voltage on unselected cells, the patent eliminates program disturb on neighboring cells while maintaining the high-density parasitic capacitance coupling structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturb on unselected cells while maintaining the programming efficiency of selected cells by creating a larger voltage swing and isolating the channel of the selected word line from unselected word lines during programming.
Implementation Method 1
parasitic capacitance coupling between the selected word line and adjacent word lines becomes problematic
Implementation Method 2
biasing unselected word lines with a negative voltage before transitioning to Vpass, coupled with a positive well voltage, creating a larger voltage swing on the source and drain regions of unselected cells
Data Source
AI summary
The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential.