Neighbor Word Line Compensation for Memory Programming
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Solution Overview
Problem
The shrinking size of memory circuitry in non-volatile semiconductor memory devices leads to increased neighbor word line interference (NWI), causing challenges in programming efficiency and data retention, as the reduced physical space between word lines results in stronger NWI effects and degraded threshold voltage margins, especially during high temperature data retention.
Innovation Solution
A neighboring word line compensation full sequence program scheme is implemented, which adjusts bit line bias and sense time during program verify operations based on the voltage threshold states of neighboring word lines to compensate for interference, allowing for more precise programming and reduced program execution time by skipping unnecessary verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory circuitry size is shrunk to increase storage density, then storage capacity is improved, but neighbor word line interference increases causing degraded threshold voltage margins
Solution Approach 1:
The patent applies preliminary action by determining data states of neighboring word line memory cells before performing programming operations on the selected word line. This advance knowledge allows the system to pre-calculate appropriate bit line voltage biases that will compensate for anticipated interference effects, thereby maintaining threshold voltage margins despite reduced physical spacing between word lines.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting bit line voltage bias levels based on the determined data states of neighboring word line cells. The system modifies programming parameters (voltage bias and sense time) according to the interference conditions created by adjacent word lines, enabling precise compensation that maintains reliable programming even in high-density configurations where word lines are closely spaced.
2Speed
If conventional programming operations are performed without compensation, then programming speed is maintained, but threshold voltage distribution widens reducing programming precision
Solution Approach 1:
The patent applies parameter changes by adjusting bit line voltage bias and sense time based on neighboring word line data states. This dynamic parameter adjustment narrows threshold voltage distributions during programming without significantly impacting programming speed, as the compensation is calculated and applied efficiently during the programming sequence.
Solution Approach 2:
The patent implements feedback by using the determined data states of neighboring word line cells to inform and adjust the programming parameters of the selected word line. This feedback mechanism allows the system to compensate for interference effects in real-time, maintaining narrow threshold voltage distributions while preserving programming speed through efficient feedback-based parameter optimization.
3Manufacturing precision
If additional verify operations are performed to compensate for interference, then programming precision is improved, but program execution time increases
Solution Approach 1:
The patent applies preliminary action by determining neighboring word line data states in advance, before the programming operation begins. This pre-determination allows the system to calculate appropriate compensation parameters upfront, eliminating the need for additional verify operations while maintaining programming precision through pre-computed bit line voltage biases and sense time adjustments.
Solution Approach 2:
The patent implements skipping by eliminating unnecessary verify operations through the use of compensation based on pre-determined neighboring data states. By calculating appropriate bit line voltage biases in advance, the system can skip redundant verify steps that would otherwise be needed to correct for interference, thereby maintaining programming precision while reducing overall program execution time.
Data Source
AI summary
A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to determine data states for a first set of memory cells of a neighboring word line of the set of word lines, determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell for each memory cell of the second set of memory cells, and perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells.