Nested Acceleration System with Dynamic Module Configuration

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Solution Overview

Problem

Conventional network devices in 5G networks require various hardware acceleration cards, leading to high costs and suboptimal performance, as different devices necessitate different acceleration types and hierarchies for efficient processing.

Innovation Solution

An acceleration system comprising modular components like CPUs, GPUs, FPGAs, and ASICs, dynamically configured using a recurrent structural causal model to optimize processing based on input data, allowing for nested hardware utilization and adaptive acceleration type and hierarchy adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If different hardware acceleration types are deployed on different network devices, then processing performance is improved, but hardware acceleration costs increase

Engineering Contradiction:
Improveprocessing performanceVSAvoidhardware acceleration costs
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a unified acceleration system where a single network device can perform multiple acceleration functions (baseband processing, security, firewall) through dynamically configurable modules. This eliminates the need for separate specialized devices, reducing hardware costs while maintaining processing performance through software-defined functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The acceleration system employs dynamic configuration where the number, types, and hierarchies of acceleration modules can be adjusted in real-time based on processing needs. This allows the system to optimize performance for different workloads without requiring fixed specialized hardware for each function, thereby reducing overall hardware investment.

Inventive Principle:
Principle #15Dynamics

2Speed

If specialized acceleration cards are added to network devices, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The acceleration system is divided into independent, modular acceleration units (baseband processing module, security module, firewall module) that can be selectively activated. Each module handles specific processing tasks, allowing the system to achieve high processing speeds for particular functions without requiring all modules to be permanently installed, thus reducing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a hierarchical acceleration architecture where acceleration modules are nested within the network device structure. The first network device contains multiple acceleration modules that can be dynamically configured, creating a nested structure that optimizes processing speed while managing complexity through organized hierarchical layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11789894B2Acceleration system and dynamic configuration method thereof
Publication Date: 2023.10.17 WISTRON CORP
  • US11789894B2 patent drawing
  • US11789894B2 patent drawing
  • US11789894B2 patent drawing

AI summary

An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least another of the plurality of modules such that the acceleration system is structural and nested.