Nested Second-Order Allpass Filter With Shared Delay Elements

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Solution Overview

Problem

Existing digital all-pass filters for digital signal processing face challenges in reducing computational complexity, which leads to increased latency and cost, while maintaining signal quality and real-time processing requirements.

Innovation Solution

The proposed solution involves nesting first and second-order filters within each other, using a single delay element to replace two resulting delay elements, thereby reducing the number of delay operations and maintaining the same transfer function and coefficient mapping, while allowing independent control of pole frequencies and radii.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional lattice filter designs (Regalia, Gray-Markel) are used, then signal processing quality is maintained, but computational complexity increases with more multiplications and additions

Engineering Contradiction:
Improvesignal processing qualityVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies nesting by placing a first-order all-pass filter inside a second-order all-pass filter structure. The nested first-order filter shares delay elements with the outer second-order filter, creating a compact structure that reduces the total number of computational operations while maintaining the all-pass filter characteristics and signal processing quality.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent makes delay elements serve multiple functions simultaneously. The same delay elements are used by both the inner first-order filter and the outer second-order filter, allowing a single delay element to perform what would traditionally require separate delay elements in non-nested structures. This multi-functionality reduces the total component count and computational complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of time

If faster processing is used to reduce latency, then real-time processing capability is improved, but cost increases due to faster circuitry requirements

Engineering Contradiction:
ImprovelatencyVSAvoidcircuitry cost
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent changes the structural parameters of the filter by nesting filters and sharing delay elements, which reduces the total number of computational operations. This parameter change allows the filter to process signals faster with the same hardware resources, effectively reducing latency without requiring more expensive faster circuitry.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If simpler processing processes are employed to reduce cost, then device complexity is reduced, but signal processing quality and performance significantly deteriorate

Engineering Contradiction:
Improveprocessing complexityVSAvoidsignal processing quality
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The nested filter structure achieves simplicity by combining multiple filter orders into a unified structure that shares resources. Rather than implementing separate first-order and second-order filters independently (which would increase complexity), the nesting approach consolidates them into a single efficient structure that maintains signal processing quality while reducing operational complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS8521798B2Second order real allpass filter
Publication Date: 2013.08.27 VIDEO SOLUTIONS PTE LTD
  • US8521798B2 patent drawing
  • US8521798B2 patent drawing
  • US8521798B2 patent drawing

AI summary

A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.