Nested CAA DRAM Cell Layout for Higher Storage Density
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Solution Overview
Problem
The transition to the planar 2T0C structure in DRAM results in low storage density and a complex manufacturing process.
Innovation Solution
A memory device with a substrate and storage layer featuring Channel-All-Around (CAA) read and write transistors, where the write transistor is partially nested within the read transistor's gate groove, reducing the horizontal and vertical space occupied by the storage unit and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the planar 2T0C structure is adopted, then the manufacturing process complexity is reduced, but the storage density remains low
Solution Approach 1:
The write transistor is nested within the gate groove formed by the read transistor's gate electrode structure. Specifically, the write transistor's gate electrode is positioned inside the gate groove, and its semiconductor layer contacts the gate groove walls, creating a nested configuration that reduces overall device footprint while maintaining both transistor functionalities.
Solution Approach 2:
The invention transitions from a purely planar arrangement to a three-dimensional structure by extending the gate electrode vertically to form a gate groove, and positioning the write transistor components within this vertical space. This dimensional change allows overlapping of transistor structures in the vertical dimension, increasing storage density without proportionally increasing manufacturing complexity.
2Quantity of substance
If the storage unit volume is reduced, then the storage density is enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The gate groove is formed first as a pre-defined structure before introducing the write transistor components. The read transistor's gate electrode is formed and etched to create the gate groove, which then serves as a template and containment structure for subsequent write transistor fabrication steps, ensuring precise positioning without requiring high-precision direct alignment.
Solution Approach 2:
The gate groove acts as an intermediary structure that mediates the spatial relationship between the read and write transistors. It provides a physical boundary and positioning reference that simplifies the manufacturing process by eliminating the need for complex direct alignment between the two transistors, thus reducing precision requirements while enabling compact integration.
Data Source
AI summary
A memory includes a substrate and at least one storage layer. The storage layer is formed on the substrate, and the storage layer includes storage units. Each storage unit includes: a read transistor and a write transistor, the read transistor includes a first gate electrode, a first semiconductor layer, and a first gate insulating layer formed between the first gate electrode and the first semiconductor layer. The first gate electrode includes a gate bottom wall and a gate sidewall. The gate sidewall and the gate bottom wall enclose to form a gate groove. The write transistor includes a second gate electrode, a second semiconductor layer, and a second gate insulating layer formed between the second gate electrode and the second semiconductor layer. A part of the second semiconductor layer is embedded in the gate groove and is in contact with at least a part of the gate groove.