Nested Electronic Packaging for Compact Multi-Chip Integration
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Solution Overview
Problem
Current multi-chip integration architectures result in larger form factors that are not suitable for certain applications, and there is a need for improved signal integrity and reduced footprint in electronic packaging.
Innovation Solution
The integration of dies and components in cavities within a base substrate, utilizing through substrate vias and mold layers to optimize signal paths and reduce overall package size, with components positioned at least partially within the footprint of the dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip integration architectures are used to increase performance, then functional capability is improved, but form factor increases
Solution Approach 1:
The patent embeds components within cavities formed in the base substrate, nesting them underneath the dies. This allows multiple functional elements to be integrated in a three-dimensional arrangement rather than a planar layout, increasing performance while maintaining a compact form factor.
Solution Approach 2:
The invention transitions from a two-dimensional planar arrangement of chips to a three-dimensional structure by forming cavities in the base substrate and placing components within them. This vertical integration reduces the horizontal footprint while accommodating multiple functional elements.
2Ease of manufacture
If components are placed outside the die footprint, then ease of manufacture is improved, but signal path length increases
Solution Approach 1:
Components are nested within cavities that are positioned within or overlapping the die footprint. This arrangement minimizes the distance between dies and components while still allowing for standardized manufacturing processes for cavity formation and component placement.
Data Source
Figure 1A~1C
Figure 1D
Figure 1E
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.