Nested Multi-Chip Packaging for Smaller Footprint and Signal Integrity
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Solution Overview
Problem
Current multi-chip packaging architectures result in larger form factors that are not suitable for all use cases, failing to meet the demands for reduced size and optimized signal integrity.
Innovation Solution
The implementation of multi-chip packaging architectures with dies attached to a base substrate and components embedded in cavities within the substrate, reducing the overall footprint and signal path length, thereby improving form factor and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-chip integration architectures are implemented, then performance is improved and different process nodes can be integrated, but form factor increases making it unsuitable for compact applications
Solution Approach 1:
The patent embeds components within cavities formed in the base substrate, creating a nested structure where components are positioned inside the substrate volume rather than occupying additional planar space. This allows multiple chips and components to be integrated vertically within the footprint of a single chip, reducing overall form factor while maintaining multi-chip integration capabilities
Solution Approach 2:
The invention transitions from traditional planar multi-chip arrangements to a three-dimensional architecture by forming cavities within the base substrate and positioning components within these cavities. This vertical integration approach utilizes the Z-dimension to reduce the X-Y footprint while maintaining signal integrity through direct coupling
2Ease of manufacture
If components are placed outside the die footprint, then manufacturing is simplified, but signal path length increases reducing signal integrity
Solution Approach 1:
Components are nested within cavities that are formed within the base substrate footprint, allowing signal paths to remain short while maintaining the manufacturing advantages of separate component fabrication. The cavity structure enables components to be positioned effectively within the die area without requiring complex co-fabrication processes
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.