Nested Clock Driver Circuits for Wide-Range Duty Cycle Correction

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Solution Overview

Problem

Existing digital duty cycle correction (DCC) loops suffer from the least significant bit (LSB) step size problem, which affects their ability to accurately correct duty cycle errors over wide frequency ranges, such as those required for DDR memory systems.

Innovation Solution

A clock driver circuit with nested driver circuits and a correction logic circuit, where each nested driver circuit is designed for a specific frequency range, allowing for duty cycle correction across a wide frequency range without the limitations of the LSB step size issue.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single digital DCC loop is used, then the circuit is simple, but it cannot accurately correct duty cycle errors across wide frequency ranges due to the LSB step size problem

Engineering Contradiction:

Improveduty cycle correction accuracyVSAvoidfrequency range coverage

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent divides the frequency range into multiple segments (first frequency range and second frequency range) and assigns different driver circuits to each segment. Each driver circuit has parameters optimized for its specific frequency range, allowing accurate duty cycle correction across the entire wide frequency spectrum without the LSB step size problem that plagues single-loop designs.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic parameter selection where the correction logic circuit automatically selects which driver circuit to use based on the detected frequency range. This dynamic adaptation ensures that the system always uses the optimally tuned parameters for the current operating frequency, maintaining high correction accuracy across all frequencies.

Inventive Principle:

Principle #15Dynamics

2Measurement precision

If multiple driver circuits are used for different frequency ranges, then duty cycle correction accuracy improves across wide frequency ranges, but the device area increases

Engineering Contradiction:

Improveduty cycle correction accuracyVSAvoidcircuit area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent implements a nested architecture where the second driver circuit is nested within the first driver circuit structure. This nesting allows shared resources such as common input/output paths, control logic, and infrastructure elements, reducing the total area required compared to completely separate circuits while maintaining the benefits of frequency-range-specific parameter optimization.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12212322B2Clock driver with duty cycle correction

Publication Date: 2025.01.28 ADVANCED MICRO DEVICES INC

AI summary

A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.