Nested Dielectric Layer Structure for Low-Capacitance Source/Drain Regions
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce parasitic capacitance between source/drain features and gate while maintaining desired K values, which becomes increasingly difficult as device geometry scales down.
Innovation Solution
The solution involves forming a dielectric layer structure with specific film properties over exposed surfaces of sacrificial gate structures and semiconductor layers, which includes a first dielectric layer in contact with inner spacers and a second dielectric layer nested within the first, to reduce source/drain leakage and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is scaled down to increase functional density, then production efficiency and cost are improved, but parasitic capacitance between source/drain features and gate increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between the source/drain features and the gate electrode. This dielectric layer acts as a mediator that reduces the parasitic capacitance coupling between these components while allowing the device to maintain scaled-down dimensions for high functional density.
Solution Approach 2:
The dielectric layer is selectively positioned in regions where parasitic capacitance is most problematic - specifically between the source/drain features and the gate electrode. This localized approach targets the harmful capacitance effect without affecting other device regions, allowing different parts of the device to have optimized properties for their specific functions.
2Productivity
If device geometry is scaled down to increase functional density, then production efficiency and cost are improved, but maintaining desired K value becomes more difficult
Solution Approach 1:
The dielectric layer modifies the electrical parameters of the device by changing the capacitance characteristics between source/drain and gate. This parameter change allows the device to maintain the desired K value (drive current) even when scaled down, as the dielectric properties can be tuned to compensate for size reduction effects.
3Object-affected harmful factors
If a dielectric layer is added to reduce parasitic capacitance, then parasitic capacitance and source/drain leakage are reduced, but device structure complexity increases
Solution Approach 1:
The dielectric layer is segmented into specific regions rather than being a continuous layer throughout the device. It is positioned only where needed to reduce parasitic capacitance - specifically in the regions between source/drain features and gate electrode - which simplifies the overall structure compared to a comprehensive dielectric solution while still achieving the desired effect.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate. The dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.