Nested Erasure Coding for Flash Array Hard Error Recovery

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Solution Overview

Problem

Flash storage devices face challenges in data protection due to higher likelihood of hard errors compared to hard disk drives, especially near the end of their write endurance or data retention life, which can lead to device failures and data loss when combined with catastrophic failures, making existing RAID systems like RAID 5 and RAID 6 inefficient in handling these errors.

Innovation Solution

The implementation of nested multiple erasure correcting codes that encode data using horizontal and vertical erasure codes, allowing recovery from multiple erasures across rows and columns in a storage array, thereby providing efficient protection against both device and block failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If RAID 5 is used to protect against single catastrophic disk failure, then storage efficiency is improved, but reliability deteriorates when latent hard errors occur in flash devices

Engineering Contradiction:
Improvestorage efficiencyVSAvoiddata protection against latent hard errors
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the data protection approach by implementing row-level and device-level parity separately. Each row has its own parity page for correcting single erasures within that row, while additional device-level parity pages provide protection across multiple rows. This segmentation allows the system to maintain RAID 5 efficiency for single failures while adding RAID 6-like protection against multiple latent errors without requiring full RAID 6 redundancy throughout.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different levels of protection at different scopes: row-level parity for local single-erasure correction and device-level parity for global multiple-erasure protection. This allows the system to optimize storage efficiency at the row level while maintaining reliability at the device level, resolving the contradiction between efficiency and protection.

Inventive Principle:
Principle #3Local quality

2Reliability

If RAID 6 is used to protect against double catastrophic disk failure, then reliability is improved, but storage efficiency deteriorates

Engineering Contradiction:
Improvedata protection against multiple failuresVSAvoidstorage efficiency
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the redundancy mechanism into optional row-level parity (for single erasures) and mandatory device-level parity (for multiple erasures). This allows the system to achieve RAID 6 reliability for the critical case of multiple latent errors while maintaining RAID 5 efficiency for normal operation, by only applying full RAID 6 protection where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by implementing device-level parity only when multiple erasures are detected across different rows, rather than requiring full RAID 6 protection for all cases. This partial application of redundancy provides sufficient protection against the most severe failures while minimizing overhead for typical single-failure scenarios.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If more parity pages are added to correct multiple erasures, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidencoding and decoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction process into two independent stages: row-level correction for single erasures and device-level correction for multiple erasures. This segmentation simplifies the overall complexity by breaking down the correction algorithm into manageable steps, where each stage handles a specific scope of failures independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by first attempting row-level parity correction for single erasures before proceeding to device-level parity correction for multiple erasures. This staged approach simplifies the decoding process by handling the most common single-failure case first, then only engaging the more complex device-level correction when necessary.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20120331367A1Nested Multiple Erasure Correcting Codes for Storage Arrays
Publication Date: 2012.12.27 SK HYNIX INC
  • US20120331367A1 patent drawing
  • US20120331367A1 patent drawing
  • US20120331367A1 patent drawing

AI summary

Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r-1 rows, up to tr-2 erasures in any one of the remaining r-2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.