Nested ESD Circuit Protects Core Without Area Penalty
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Solution Overview
Problem
Conventional electrostatic discharge immunizing circuits in chips are ineffective in completely protecting core circuits from electrostatic discharges and result in area penalties when additional circuits are added to prevent errors, especially in analog circuits where the core circuit is sensitive to discharges.
Innovation Solution
An electrostatic discharge immunizing circuit is designed with a core circuit, a main immunizing circuit surrounding it, and a secondary immunizing circuit between them, utilizing power clamps and current limiters biased with independent voltage sources and grounds to direct electrostatic discharges away from the core circuit without increasing the chip's area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional ESD immunizing circuits are added around the chip to completely discharge electrostatic discharges, then the protection reliability is improved, but the chip area increases
Solution Approach 1:
The ESD immunizing circuit is divided into two parts: a main ESD immunizing circuit disposed at the surroundings of the chip and a secondary ESD immunizing circuit disposed between the core circuit and the main ESD immunizing circuit. This segmentation allows the secondary circuit to provide additional protection specifically for the core circuit without requiring a complete redesign of the entire ESD protection system, thereby improving protection reliability while minimizing area increase.
Solution Approach 2:
The secondary ESD immunizing circuit is strategically placed only between the core circuit and the main ESD immunizing circuit, providing localized enhanced protection where it is most needed. This local quality approach ensures that the core circuit, which is most sensitive to ESD, receives additional protection without requiring additional circuits throughout the entire chip, thus avoiding excessive area penalties.
2Reliability
If the core circuit is disposed at the center of the chip to maximize distance from ESD sources, then the protection effectiveness is improved, but the area available for other circuits is reduced
Solution Approach 1:
The secondary ESD immunizing circuit is nested between the core circuit and the main ESD immunizing circuit, creating a layered protection structure. This nesting allows the core circuit to remain at the center for optimal protection while the secondary circuit utilizes the space in the intermediate region, effectively using otherwise wasted space and avoiding area penalties.
3Volume of stationary object
If the core circuit volume is reduced to minimize chip size, then the chip volume is reduced, but the sensitivity to electrostatic discharges increases
Solution Approach 1:
The secondary ESD immunizing circuit is configured in advance to provide preliminary protection to the core circuit before electrostatic discharges can reach it. The power clamps and current limiters are pre-positioned to detect and divert ESD currents, creating a protective barrier that activates automatically when ESD events occur, thus protecting the compact core circuit without requiring it to be larger.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively protects the core circuit from electrostatic discharges without the area penalties associated with additional immunizing circuits, ensuring accurate calculations and reducing erroneous signals in both analog and digital chip operations.
Implementation Method 1
an electrostatic discharge immunizing circuit is conventionally disposed in the chip for discharging the released electrostatic discharges by providing discharging paths
Implementation Method 2
The first current limiter has a positive bias terminal coupled to a signal input terminal, and has a negative bias terminal coupled to the first voltage source
Data Source
AI summary
A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp.