Nested Hash Memory Optimization via Register Reuse

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Solution Overview

Problem

Existing cryptographic procedures that perform nested hash operations require additional memory to store intermediate hash values, which can be inefficient in terms of memory usage, especially in integrated circuit implementations.

Innovation Solution

The proposed solution optimizes memory usage by storing the first hash value in the output stage registers until a portion of the message scheduling stage registers is not used during the second hash operation, thereby eliminating the need for an additional buffer memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional buffer memory is used to store intermediate hash values during nested hash operations, then the reliability of the cryptographic procedure is improved, but the device complexity and memory requirements increase

Engineering Contradiction:
Improvecryptographic procedure reliabilityVSAvoidmemory structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The message scheduling stage registers are designed to serve dual purposes: storing message blocks during hash operations and storing intermediate hash values when needed. This multi-functional design eliminates the need for dedicated buffer memory while maintaining the reliability of nested hash operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the buffer memory function into the existing message scheduling stage registers by utilizing unused register slots. Instead of adding separate buffer memory components, the intermediate hash values are stored in the same register file used for message scheduling, thereby combining storage functions and reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If buffer memory is added to store intermediate hash values, then the productivity of nested hash operations is improved, but the loss of substance (memory resources) increases

Engineering Contradiction:
Improvenested hash operation throughputVSAvoidmemory resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system dynamically allocates register usage based on operational phase: during message processing, registers store message blocks; during intermediate storage phases, the same registers store hash values. This dynamic reuse of memory resources enables efficient nested hash operations without requiring additional static memory allocation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The message scheduling stage registers are temporarily used to store intermediate hash values and then recovered for subsequent message processing. This temporary borrowing and returning of register resources allows the system to handle nested hash operations efficiently without permanently allocating additional memory.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS11539509B2Memory optimization for nested hash operations
Publication Date: 2022.12.27 CRYPTOGRAPHY RESEARCH INC
  • US11539509B2 patent drawing
  • US11539509B2 patent drawing
  • US11539509B2 patent drawing

AI summary

Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.