Nested Inter-Substrate Interconnects for Dense EMI-Shielded Packaging

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Solution Overview

Problem

There is an ongoing need for packages with improved performance and reduced size, particularly in the integration of substrates and integrated devices.

Innovation Solution

A package design incorporating a first substrate with integrated devices connected via solder interconnects, an inter substrate interconnect structure with an inner interconnect and dielectric layer, and a second substrate connected through additional solder interconnects, surrounded by an encapsulation layer, which facilitates high-density interconnects and improved electrical paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If traditional substrate integration methods are used, then manufacturing is simpler, but package size is larger and performance is limited

Engineering Contradiction:
Improvepackage sizeVSAvoidinterconnect structure complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent implements nested interconnect structures where inner interconnects are positioned within outer interconnects, allowing multiple signal paths to occupy the same spatial footprint. This nesting arrangement reduces the overall package volume while maintaining complex interconnect functionality, directly resolving the contradiction between compact size and structural complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from planar interconnect arrangements to three-dimensional stacked configurations with inner and outer interconnect layers at different heights. By utilizing the vertical dimension, the design achieves higher interconnect density without increasing the lateral package footprint, thereby reducing package size while managing complexity through structured layering.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If more interconnect paths are added to improve performance, then electrical paths increase, but cross-talk and electromagnetic interference increase

Engineering Contradiction:
Improveelectrical path densityVSAvoidcross-talk and electromagnetic interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces dielectric layers as intermediary materials between inner and outer interconnects. These dielectric layers act as electromagnetic shields and isolation barriers, preventing cross-talk and interference between adjacent signal paths while allowing high-density interconnect routing. This mediator approach enables increased electrical path density without proportionally increasing harmful electromagnetic effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent strategically positions outer interconnects to serve dual functions: as signal carriers and as electromagnetic shields for inner interconnects. By converting the potential harmful effect of closely spaced interconnects into a beneficial shielding arrangement, the design achieves high interconnect density while naturally suppressing cross-talk and electromagnetic interference through the geometric configuration itself.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances performance by increasing electrical paths, reducing package size, minimizing cross-talk, and optimizing power distribution while providing electromagnetic interference shielding.

Implementation Method 1

a dielectric layer coupled to the inner interconnect

Methodology Applied
Scientific EffectDielectric: Dielectric

Implementation Method 2

an integrated device coupled to the first substrate through at least a first plurality of solder interconnects

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS20250273612A1Package comprising a substrate including an inter substrate interconnect structure comprising an inner interconnect
Publication Date: 2025.08.28 QUALCOMM INC
  • US20250273612A1 patent drawing
  • US20250273612A1 patent drawing
  • US20250273612A1 patent drawing

AI summary

A package comprising a first substrate; an integrated device coupled to the first substrate through at least a first plurality of solder interconnects; an inter substrate interconnect structure coupled to the first substrate through at least a second plurality of solder interconnects. The inter substrate interconnect structure comprises an inner interconnect; a dielectric layer coupled to the inner interconnect; and an interconnect coupled to the dielectric layer, wherein the interconnect surrounds the dielectric layer and the inner interconnect; a second substrate coupled to the inter substrate interconnect structure through at least a third plurality of solder interconnects; and an encapsulation layer coupled to the first substrate and the second substrate.