Nested Interposer Package for Fine-Pitch Alignment and Warpage
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Solution Overview
Problem
Current multi-chip integration architectures result in larger form factors and suffer from poor yield and reliability due to alignment issues and warpage in traditional packaging substrates, particularly in multi-die systems.
Innovation Solution
The use of heterogeneous nested interposers with cavities that house nested components, utilizing intermediate pads and vias to correct misalignment between interposer and nested components, enabling precise interconnects even with fine pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip integration architectures are used to increase performance and reduce form factor, then device functionality is improved, but manufacturing precision deteriorates due to alignment issues and warpage
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between multiple dies. The interposer provides a stable reference plane and standardized interconnect interface, mediating the alignment between dies manufactured at different process nodes. This intermediary structure absorbs and compensates for dimensional variations and warpage, enabling precise alignment without requiring direct die-to-die alignment precision.
Solution Approach 2:
The patent utilizes controlled thermal expansion parameters by selecting interposer substrate materials with specific coefficients of thermal expansion (CTE) that match those of the attached dies. By carefully controlling the CTE parameter and thermal processing conditions, the patent minimizes thermally-induced warpage and maintains alignment precision during packaging and operation.
2Ease of manufacture
If traditional packaging substrates are used in multi-die systems, then ease of manufacture is maintained, but reliability deteriorates due to warpage and alignment issues
Solution Approach 1:
The patent applies local quality enhancement by creating cavities in the interposer substrate at specific locations where nested components are positioned. This localized structural modification provides mechanical support and stress relief precisely where needed, preventing warpage in critical areas while maintaining the overall ease of manufacture through standardized interposer fabrication processes.
Solution Approach 2:
The patent implements a nested architecture where nested components (such as passive components or additional dies) are placed within cavities of the interposer substrate. This nesting approach improves reliability by distributing mechanical stresses and reducing warpage, while maintaining manufacturing ease through a hierarchical assembly process where components are added in stages.
3Volume of moving object
If finer pitch interconnects are used to reduce form factor, then volume is reduced, but manufacturing precision requirements increase due to alignment sensitivity
Solution Approach 1:
The interposer substrate acts as a mediator that decouples the alignment requirements between fine-pitch interconnects on dies and the overall package geometry. By providing a rigid reference plane with precisely positioned interconnect structures, the interposer enables fine-pitch connections to be formed with relaxed global alignment tolerances, as local alignment at the interposer interface can be controlled more precisely.
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.