Nested Interposer Package for Fine-Pitch Multi-Chip Alignment
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Solution Overview
Problem
Current multi-chip integration architectures result in larger form factors and suffer from poor yield and reliability due to misalignment and warpage issues in interconnections between dies.
Innovation Solution
The use of heterogeneous nested interposers with cavities that house nested components, utilizing intermediate pads and vias to correct misalignment and provide improved alignment between interposer and nested component pads, allowing for fine-pitched interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-chip integration architectures are used to increase performance and reduce form factor, then device performance and integration density are improved, but manufacturing yield and reliability deteriorate due to misalignment and warpage issues in interconnections
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between multiple chips. The interposer includes intermediate pads that serve as a mediator layer, enabling separate alignment processes for each chip-to-interposer connection. This intermediary structure eliminates the need for direct multi-chip alignment, thereby resolving the misalignment and warpage issues that reduce manufacturing yield and reliability.
2Device complexity
If direct multi-chip interconnection is implemented, then device complexity is reduced, but manufacturing precision deteriorates due to cumulative alignment errors between multiple dies
Solution Approach 1:
The patent segments the interconnection structure into two separate stages: first connecting each chip to the interposer substrate, then connecting the interposer to the final substrate. This segmentation breaks down the complex multi-chip alignment problem into simpler, independent alignment steps, each with its own reference frame (the interposer), thereby eliminating cumulative alignment errors.
3Reliability
If larger package size is used to accommodate multiple chips, then manufacturing yield improves due to easier alignment, but form factor increases which is not suitable for some use cases
Solution Approach 1:
The patent employs a nested structure where multiple chips are effectively nested within the interposer substrate's footprint. The intermediate pads and cavity structures allow chips to be positioned in a compact arrangement that充分利用 the available space, achieving high integration density without increasing the overall package form factor.
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
Embodiments disclosed herein include an electronic package (100, 200, 300) comprising an interposer (130), wherein the interposer comprises a first plurality of through interposer vias (134) through the interposer; and a second plurality of through interposer vias (134) through the interposer; a nested component (140) in the interposer, wherein the nested component is between the first plurality of through interposer vias and the second plurality of through interposer vias, the nested component comprising a frontside , a backside and a plurality of through component vias (144) between the front side and the backside; a die (120) coupled to the first plurality of through interposer vias by first interconnects (181) and coupled to the front side of the nested component by second interconnect (182); and a redistribution layer (354) below the interposer, the redistribution layer coupled to the first plurality of through interposer vias, the second plurality of through interposer vias, and the backside of the nested component.